Semiconductor device and manufacturing method of the same
View Patent ↗After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H 2 , thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
1. A semiconductor device comprising:
a MISFET including:
a gate insulating film formed on a semiconductor substrate;
a gate electrode formed on the gate insulating film;
a source region formed in the semiconductor substrate; and
a drain region formed in the semiconductor substrate,
wherein the gate insulating film includes:
a silicon oxide layer formed on the semiconductor substrate;
an oxygen deficiency adjustment layer formed on the silicon oxide layer; and
a high dielectric constant layer formed on the oxygen deficiency adjustment layer, the high dielectric constant layer including a hafnium oxide film,
wherein the gate electrode includes a metal film formed on the high dielectric constant layer and having a reduction catalyst effect,
wherein the oxygen deficiency adjustment layer comprises an oxide containing a group 2A element, a group 3A element, a group 3B element, a group 4A element, or a group 5A element, and
wherein the gate insulating film is formed such that a dipole exists between the silicon oxide layer and the oxygen deficiency adjustment layer.
2. The semiconductor device according to claim 1 , wherein the metal film is a single layer film of platinum or rhenium, a laminated film with a platinum layer and a rhenium layer, or an alloy film formed from platinum or rhenium.
3. The semiconductor device according to claim 1 , wherein the MISFET is a p-channel MISFET.
4. The semiconductor device according to claim 1 , wherein the MISFET is an n-channel MISFET.
5. The semiconductor device according to claim 1 , wherein the oxygen deficiency adjustment layer comprises Al 2 O 3 , Y 2 O 3 , La 2 O 3 , MgO, CaO, SrO, or BaO.
6. The semiconductor device according to claim 1 , wherein the high dielectric constant layer is in contact with the oxygen deficiency adjustment layer and the gate electrode.
7. The semiconductor device according to claim 1 , wherein the MISFET has been heat treated such that the oxygen deficiency adjustment layer has a lower oxygen content than prior to the heat treatment, said lower oxygen content contributing to the dipole between the silicon oxide layer and the oxygen deficiency adjustment layer.
8. The semiconductor device according to claim 1 , wherein
the oxygen deficiency adjustment layer has a pre-heat-treatment first state and a post-heat-treatment second state,
the oxygen deficiency adjustment layer has a higher oxygen content in the first state than in the second state, and
the dipole formed between the silicon oxide layer and the oxygen deficiency adjustment layer in the second state has at least one different property than the dipole formed between the silicon oxide layer and the oxygen deficiency adjustment layer in the first state.