Dynamic random access memory device and method of determining refresh cycle thereof

1. A method of determining a refresh cycle of a dynamic random access memory device, the method comprising:

selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number greater than two, and selecting the monitoring bits comprises;

determining during an a-th self refresh cycle whether data bits stored in a memory array have errors using the data bits and error correction code (ECC) bits corresponding to the data bits, where “a” is a natural number which is equal to or greater than one and less than “n”, and

determining during an (a+1)-th self refresh cycle whether the data bits stored in the memory array have errors using the data bits and the ECC bits corresponding to the data bits when no errors occurred in the data bits during the a-th self refresh cycle, wherein the (a+1)-th self refresh cycle is longer than the a-th self refresh cycle;

detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and

adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.

2. The method of claim 1 , wherein the selecting of the monitoring bits further comprises, when data bits having errors are detected, defining the data bits having the errors as monitoring bits and storing addresses of the monitoring bits in a monitoring address storage unit.

3. The method of claim 1 , wherein, in the adjusting of the (m+1)-th self refresh cycle, the (m+1)-th self refresh cycle is reduced when at least some of the monitoring bits have errors.

4. The method of claim 1 , wherein, in the adjusting of the (m+1)-th self refresh cycle, the (m+1)-th self refresh cycle is increased when the monitoring bits are normal.

5. A dynamic random access memory device comprising:

an ECC engine configured to select one or more monitoring bits during a self refresh period and detect whether the selected monitoring bits have errors,

wherein the ECC engine is further configured to select the monitoring bits during first through n-th self refresh cycles, detect whether the selected monitoring bits have errors during (n+1)-th through m-th self refresh cycles, and adjust an (m+1)-th self refresh cycle according to whether the selected monitoring bits have errors, wherein “n” is a natural number equal to or greater than one, and “m” is a natural number equal to or greater than n+1;

a monitoring address storage unit configured to store monitoring addresses of the selected monitoring bits; and

a refresh cycle determining circuit configured to adjust a self refresh cycle according to whether the selected monitoring bits have errors.

6. The memory device of claim 5 , wherein “n” is a natural number greater than two, and the ECC engine is further configured to determine during an a-th self refresh cycle whether data bits stored in a memory array have errors using the data bits and ECC bits corresponding to the data bits and,

when no errors occurred in the data bits during the a-th self refresh cycle, the ECC engine is further configured to determine during an (a+1)-th self refresh cycle whether the data bits stored in the memory array have errors using the data bits and the ECC bits corresponding to the data bits, wherein “a” is a natural number which is equal to or greater than one and less than “n”, and the (a+1)-th self refresh cycle is longer than the a-th self refresh cycle.

7. The memory device of claim 5 , wherein the refresh cycle determining circuit is further configured to reduce the (m+1)-th self refresh cycle when at least some of the monitoring bits have errors and to increase the (m+1)-th self refresh cycle when the monitoring bits are normal.

8. The memory device of claim 5 , wherein the monitoring address storage unit comprises:

a plurality of monitoring address registers storing the monitoring addresses;

a plurality of sampling flag registers corresponding to the monitoring address registers, respectively, and storing sampling flags, each indicating whether one of the monitoring addresses is stored in a corresponding one of the monitoring address registers; and

a plurality of error flag registers corresponding to the monitoring address registers, respectively, and storing error flags, each indicating whether one of the monitoring bits, which correspond respectively to the monitoring addresses stored in the monitoring address registers, has an error.

9. The memory device of claim 5 , wherein the monitoring address storage unit is of a volatile type.