Flat-panel display device
View Patent ↗According to an embodiment of the invention, even if a sample-and-hold circuit samples a signal from a signal processor to a display unit, an image quality reduction is hard to occur. According to an embodiment of the invention, there is provided a flat-panel display device includes a phase control circuit setting a state that a first parallel arrangement RGB pixel signal shifts by 120 degrees, a sample-and-hold circuit sampling a second parallel arrangement RGB pixel signal parallel-output from the phase control circuit to obtain a series arrangement RGB pixel signal, which is three times as much as a single pixel signal, and a driver supplying the series arrangement RGB pixel signal to the corresponding display pixel.
1. A flat-panel display device comprising:
a phase control circuit setting a state that a first parallel arrangement RGB pixel signal shifts by 120 degrees;
a sample-and-hold circuit sampling a second parallel arrangement RGB pixel signal parallel-output from the phase control circuit to obtain a series arrangement RGB pixel signal, which is three times as much as a single pixel signal; and
a driver supplying the series arrangement RGB pixel signal to the corresponding display pixel, the driver setting some pairs of RG pixel signal, BR pixel signal, GB pixel signal, RG pixel signal, BR pixel signal, GB pixel signal, . . . when supplying the series arrangement RGB pixel signal to the corresponding display pixel, and supplying one pixel signal of each pair to the corresponding display pixel in an n (n being an integer) frame while supplying the other pixel signal of each pair to the corresponding display pixel in a (n+1) frame.
2. The device according to claim 1 , wherein the display area driver supplies the series arrangement RGB pixel signal to the corresponding display pixel, the driver setting some pairs of RG pixel signal, BR pixel signal, GB pixel signal, RG pixel signal, BR pixel signal, GB pixel signal, . . . when supplying the series arrangement RGB pixel signal to the corresponding display pixel, and supplies one pixel signal of each pair to the corresponding display pixel in an n frame while supplies the other pixel signal of each pair to the corresponding display pixel in a (n+1) frame,
One and the other pixel signals are selected so that the pixel signal shifts in a horizontal direction between vertical and horizontal lines in the same frame.
3. The device according to claim 1 , wherein the phase control circuit sets a state that an output of a digital-to-analog converter, that is, first parallel arrangement RGB pixel signal shifts by 120 degrees in its phase.
4. The device according to claim 1 , wherein the phase control circuit sets a state that a digital signal, that is, parallel arrangement RGB pixel signal shifts by 120 degrees, and supplies the signal to an analog-to-digital converter.
5. The device according to claim 1 , further comprising:
a conversion circuit separating and parallelizing a digital video signal having YUV components series-sent at a first frequency (f) clock every component to obtain a parallel data stream having a second frequency (f/N) clock, and carrying out an operation using the parallel data stream to generate a parallelized first intermediate parallel RGB signal;
an interpolation circuit arranging a second intermediate parallel RGB signal having the same content neighboring the first intermediate parallel RGB signal in its time axis, and arranging front and read parallel RGB signals generated by an interpolation processing in the time axis of the first and second intermediate parallel RGB signals, and further, outputting the front parallel RGB signal, first, second intermediate parallel RGB signals and the rear parallel RGB signal; and
a digital-to-analog converter converting the front parallel RGB signal, first, second intermediate parallel RGB signals and the rear parallel RGB signal to an analog signal every R series, G series and B series, and outputting the output at the first frequency (f),
the output from the digital-to-analog converter being input to the phase control circuit.
6. The device according to claim 5 , wherein the sample-and-hold circuit samples and holds the front parallel RGB signal, first, second intermediate parallel RGB signals and the rear parallel RGB signal, which are output from the phase control circuit and supplied at the first frequency (f) according to a third frequency (f/N2) for converting the number of pixels.
7. The device according to claim 5 , further comprising: a first switch; the first switch directly supplying an output signal from the conversion circuit or an output signal of the interpolation circuit to the digital-to-analog converter.
8. The device according to claim 7 , further comprising: a second switch; the second switch directly supplying an output signal from the digital-to-analog converter or an output signal of the phase control circuit to the sample-and-hold circuit.