Display substrate
View Patent ↗A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.
1. A display substrate comprising:
a base substrate including a trench pattern formed between a first contour line and at least one second contour line formed in a region defined by the first contour line;
a first line layer in the trench pattern of the base substrate;
an insulating layer on the base substrate having the first line layer to cover the first line layer;
a second line layer on the insulating layer;
a TFT on the base substrate and electrically connected to the first line layer and the second line layer; and
a pixel electrode on the base substrate electrically connected to the TFT.
2. The display substrate of claim 1 , wherein the first line layer comprises copper, silver or an alloy thereof.
3. The display substrate of claim 2 , wherein the first line layer comprises:
a seed layer on an inner surface of the trench; and
a conductive layer on the seed layer.
4. The display substrate of claim 3 , wherein the seed layer comprises at least one selected from the group consisting of copper (Cu), molybdenum (Mo), titanium (Ti), titanium oxide (TiO), tantalum (Ta), an oxide thereof and a nitride thereof.
5. The display substrate of claim 1 , wherein the first line layer comprises a gate pad in a peripheral region of the base substrate and a gate line electrically connected to the gate pad, and
the second line layer includes a source pad in the peripheral region and a source line electrically connected to the source pad.
6. The display substrate of claim 5 , wherein the first line layer is opposite to the gate pad, and further comprises a guard ring electrically connected to a plurality of gate lines.
7. The display substrate of claim 1 , wherein a distance between the first contour line and the second contour line is no more than about 200 μm.
8. The display substrate of claim 7 , wherein a depth of the trench is no more than about 5,000 Å.
9. The display substrate of claim 7 , wherein a plurality of second contour lines having a plurality of slit shapes arranged substantially in parallel with each other is formed in the first contour line defining the gate pad, and the slit shapes expose the base substrate.
10. The display substrate of claim 9 , wherein a width of each of the second contours defining the slit shapes is about 20 μm, and a distance between adjacent second contours is about 40 μm.
11. The display substrate of claim 1 , wherein the first line layer comprises a source pad in the peripheral region, and
the second line layer includes a gate pad in the peripheral region.
12. The display substrate of claim 11 , wherein the first contour line defines a shape of the source pad, and
the second contour line is extended in a direction substantially parallel with the source line and exposes the base substrate in the source pad along the source line.
13. The display substrate of claim 12 , wherein a width of each of the second contour lines is about 20 μm, and a distance between adjacent second contour lines is about 40 μm.