Address generation unit for accessing a multi-dimensional data structure in a desired pattern

1. A system comprising:

a read and write capable data memory storing a multi-dimensional data structure, and at least one processor;

a programmable address generation unit comprising programmable descriptor memory, said programmable address generation unit configured to translate connection identifiers into real addresses in order to access the multi-dimensional data structure in a desired pattern;

wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory is selected from the group consisting of point-to-point, broadcast, scatter, and gather buffer types; and

wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is selected from the group consisting of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types;

said address generation unit configured to calculate real addresses by executing a series of patterns pre-programmed by said least one processor into the address generation unit's port descriptor memory prior to accessing the multi-dimensional data structure, the address generation unit receiving as inputs a set of parameters defining characteristics of said patterns;

wherein said connection identifier comprises a predefined number of bits, and said at least one processor loads said connection identifier into said buffer descriptor memory;

said at least one processor further configured to access the multi-dimensional data structure at the real addresses calculated by the address generation unit using said patterns and said connection identifier.

2. The system of claim 1 , wherein accessing the multi-dimensional data structure by the said at least one processor includes at least one of reading from and writing to the multi-dimensional data structure.

3. The system of claim 1 , wherein at least one of said at least one the processors is a vector processor.

4. The system of claim 1 , wherein the multi-dimensional data structure is a two-dimensional data structure.

5. The system of claim 1 , wherein the multi-dimensional data structure is stored in a buffer in the read and write capable data memory.

6. The system of claim 1 , wherein said port descriptor memory is a nested loop pattern, and said set of parameters defining characteristics of said nested loop pattern further comprise the number of iterations for the loops within the nested loops.

7. The system of claim 1 , wherein said port descriptor memory is programmed by said at least one processor to be either a nested loop pattern or non-recursive pattern and said set of parameters defining characteristics of said pattern further comprise any of the dimensions of the multi-dimensional data structure, the step size for said loops within the nested loops, the dimensions of the multi-dimensional data structure, and the inheritance of the starting points of the previous loops.

8. The system of claim 1 , wherein said port descriptor memory is an end point pattern descriptor memory, and said defining characteristics of said end point pattern further comprise the end points of said end point pattern.

9. A method comprising:

providing a read and write capable data memory storing a multi-dimensional data structure, and a at least one processor;

providing a programmable address generation unit comprising programmable descriptor memory, said programmable address generation unit configured to translate connection identifiers into real addresses in order to access the multi-dimensional data structure in a desired pattern;

wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory programmable to implement any of point-to-point, broadcast, scatter, and gather buffer types; and

wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is programmable to implement any of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types;

configuring the address generation unit to calculate the real addresses by using said at least one processor to load at least one descriptor for a pattern into said port descriptor memory;

wherein said connection identifier comprises a predefined number of bits, and said at least one processor further programs the address generation unit by loading said connection identifier into said buffer descriptor memory;

and accessing the multi-dimensional data structure at the real addresses calculated by the address generation unit using said descriptor for a pattern and said connection identifier.

10. The method of claim 9 , wherein accessing the multi-dimensional data structure includes at least one of reading from and writing to the multi-dimensional data structure.

11. The method of claim 9 , wherein accessing the multi-dimensional data structure includes accessing the multi-dimensional data structure with a vector processor.

12. The method of claim 9 , wherein the multi-dimensional data structure is a two-dimensional data structure.

13. The method of claim 9 , wherein providing a multi-dimensional data structure comprises storing the multi-dimensional data structure in a buffer in the read and write capable data memory.

14. The method of claim 9 , wherein said port descriptor memory is programmed by said at least one processor to implement a nested loop pattern, and said descriptor for a pattern further comprises the number of iterations for the loops within the nested loops.

15. The method of claim 9 , wherein said port descriptor memory is programmed by said at least one processor to implement either a nested loop pattern or non-recursive pattern, and said descriptor for a pattern further comprises any of the dimensions of the multi-dimensional data structure, at least one of the step size for said loops within the nested loops, and the inheritance of the starting points of the previous loops.

16. The method of claim 9 ,

wherein said programmable address generation unit is a programmable address generation unit device that further comprises at least one custom VLSI circuit or gate array, or at least one programmable processor, or at least one programmable hardware device selected from the group consisting of field programmable gate arrays, programmable array logic, and programmable logic devices; and

wherein said programmable address generation unit device uses said method to efficiently perform at least one task selected from the group consisting of data modulation, demodulation, encryption, decryption, encoding, decoding, transcoding, processing, and analysis;

or wherein said programmable address generation unit device uses said method in programmable address generation components of one or more devices selected from the group consisting of video recording devices, audio recording devices, telecommunications devices, home gateway devices, mobile phone devices, personal digital assistant (PDA) devices, video player devices, audio player devices, and gaming devices.

17. The method of claim 9 , wherein said port descriptor memory is programmed to implement an end point pattern, and said descriptor for said end point pattern further comprise the end points of said end point pattern.

18. An apparatus comprising:

a read and write capable data memory capable of storing a multi-dimensional data structure, and at least one non-address-generation-unit processor;

a programmable address generation unit configured to translate connection identifiers into real addresses in order to access said multi-dimensional data structure in a desired pattern in said data memory,

wherein the address generation unit comprises programmable descriptor memory, and further comprises at least one custom VLSI circuit or gate array, or at least one programmable address generation unit processor, or at least one programmable hardware device selected from the group consisting of field programmable gate arrays, programmable array logic, and programmable logic devices;

wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory is selected from the group consisting of point-to-point, broadcast, scatter, and gather buffer types; and

wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is selected from the group consisting of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types;

the address generation unit configured to calculate the real addresses by executing a series of patterns pre-programmed by said at least one non-address-generation-unit processor into the address generation unit's port descriptor memory prior to accessing said multi-dimensional data structure, the address generation unit receiving as inputs from said at least one non-address-generation-unit processor, a set of descriptors defining characteristics of said pattern;

wherein said connection identifier comprises a predefined number of bits, and said at least one non-address-generation-unit-processor loads said connection identifier into said buffer descriptor memory;

wherein said non-address-generation-unit processor is configured to access the multi-dimensional data structure at the real addresses calculated by the address generation unit based upon said descriptor for a pattern and said connection identifier.

19. The apparatus of claim 18 , wherein accessing said multi-dimensional data structure by the non-address-generation unit processor includes at least one of reading from and writing to said multi-dimensional data structure.

20. The apparatus of claim 18 , said port descriptor memory comprises an end point pattern type, and said descriptors comprise the end points of said end point pattern.