Memory including a performance test circuit
A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.
1. A memory comprising:
a plurality of memory cells each comprising a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail to the true data input and to the complementary data input;
a test circuit comprising a plurality of test cells, each test cell comprising a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell to form a looped chain, each test cell comprising a first inverter connected between the true data input and the complementary data input.
2. Memory according to claim 1 , wherein a test cell also comprises a second inverter, one input of which is connected to an output of the first inverter.
3. Memory according to claim 1 wherein either
the true data input of a test cell is connected to the true bit line or
the complementary data input of a test cell is connected to the complementary bit line.
4. Memory according to claim 2 wherein either
the true data input of a test cell is connected to the true bit line or
the complementary data input of a test cell is connected to the complementary bit line.
5. Memory according to claim 1 , wherein at least one memory cell or test cell further comprises:
a true access transistor comprising a channel connected between the true data input and the input of the first inverter, and
a complementary access transistor comprising a channel connected between the complementary data input and the output of the first inverter,
wherein the true access transistor and the complementary access transistor also having a control electrode connected to a control input of the memory cell or of the test cell.
6. Memory according to claim 2 , wherein at least one memory cell or test cell further comprises:
a true access transistor comprising a channel connected between the true data input and the input of the first inverter, and
a complementary access transistor comprising a channel connected between the complementary data input and the output of the first inverter,
wherein the true access transistor and the complementary access transistor also having a control electrode connected to a control input of the memory cell or of the test cell.
7. Memory according to claim 3 , wherein at least one memory cell or test cell further comprises:
a true access transistor comprising a channel connected between the true data input and the input of the first inverter, and
a complementary access transistor comprising a channel connected between the complementary data input and the output of the first inverter,
wherein the true access transistor and the complementary access transistor also having a control electrode connected to a control input of the memory cell or of the test cell.
8. Memory according to claim 1 , wherein the test circuit also comprises an inhibition circuit to open the looped chain when it receives a test control signal.
9. Memory according to claim 2 , wherein the test circuit also comprises an inhibition circuit to open the looped chain when it receives a test control signal.
10. Memory according to claim 3 , wherein the test circuit also comprises an inhibition circuit to open the looped chain when it receives a test control signal.
11. Memory according to claim 5 , wherein the test circuit also comprises an inhibition circuit to open the looped chain when it receives a test control signal.
12. Memory according to claim 8 , wherein the inhibition circuit comprises a logic gate comprising a first input to which the test control signal is applied, a second input connected to the complementary data input of a test cell and an output connected to the true data input of a following test cell.
13. Memory according claim 1 , wherein the test circuit comprises an odd number of test cells.
14. Memory according claim 2 , wherein the test circuit comprises an odd number of test cells.
15. Memory according claim 3 , wherein the test circuit comprises an odd number of test cells.
16. Memory according claim 5 , wherein the test circuit comprises an odd number of test cells.
17. Memory according to claim 8 wherein if the inhibition circuit comprises an inverter element, the test circuit comprises an even number of test cells.
18. Memory according to claim 12 , wherein if the inhibition circuit comprises an inverter element, the test circuit comprises an even number of test cells.
19. Memory according to claim 17 , wherein the memory cells of the plurality of memory cells are grouped together in M packets of N memory cells and wherein the test circuit comprises two packets of N test cells.
20. Memory according to claim 18 , wherein the memory cells of the plurality of memory cells are grouped together in M packets of N memory cells and wherein the test circuit comprises two packets of N test cells.