Using register rename maps to facilitate precise exception semantics

1. A computing device that uses register rename maps to facilitate precise exception semantics, comprising:

a processor that supports out-of-order execution, wherein the processor includes a plurality of register rename maps that track mappings between architectural registers and physical registers for a program executing on the processor;

wherein the plurality of register rename maps include:

a working rename map that maps architectural registers associated with a decoded instruction to corresponding physical registers;

a retire rename map that tracks and preserves a set of physical registers that are associated with retired instructions; and

a checkpoint rename map that stores a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program;

wherein when the program causes an exception, the processor is configured to use the checkpoint rename map to roll back program execution to the preceding checkpoint;

wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.

2. The computing device of claim 1 , wherein the processor preserves values from the preceding checkpoint for the program in the set of physical registers until results from the checkpointed region are committed.

3. The computing device of claim 2 , wherein the processor commits a checkpointed region by:

updating the checkpoint rename map with up-to-date mappings for architectural registers from the retire rename map; and

freeing any physical registers that are no longer mapped to by an architectural register in the checkpoint rename map.

4. The computing device of claim 3 ,

wherein the processor supports a non-checkpointed mode in which individual program instructions commit immediately after executing; and

wherein the processor allows individual program instructions to commit immediately by mirroring updates to the retire rename map to the checkpoint rename map.

5. The computing device of claim 1 ,

wherein the computing device uses the plurality of register rename maps to facilitate precise exception semantics for the virtual machine.

6. The computing device of claim 5 , wherein the processor executes a subset of the program as interpreted virtual machine instructions after rolling back program execution to the preceding checkpoint.

7. The computing device of claim 1 ,

wherein additional physical registers in the processor facilitate out-of-order execution;

wherein a first subset of the architectural registers are subject to checkpointing and roll-back; and

wherein a second subset of the architectural registers are not subject to checkpointing and/or roll-back, and instead commit immediately upon the retirement of an associated instruction.

8. The computing device of claim 1 , wherein rolling back program execution to the preceding checkpoint involves discarding the results of any instructions executed after the preceding checkpoint.

9. The computing device of claim 8 , wherein discarding the results of any instructions executed after the checkpoint involves discarding values for a delayed store that executed after the preceding checkpoint.

10. A method for using register rename maps to facilitate precise exception semantics for a program, wherein the program executes on a processor that supports out-of-order execution, wherein the processor tracks mappings between architectural registers and physical registers for the program using a working rename map, a retire rename map, and a checkpoint rename map, the method comprising:

using the working rename map to map architectural registers associated with a decoded instruction to corresponding physical registers;

using the retire rename map to track and preserve a set of physical registers that are associated with retired instructions;

using the checkpoint rename map to store a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program; and

when the program causes an exception, using the checkpoint rename map to roll back program execution to the preceding checkpoint; and

wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.

11. The method of claim 10 , wherein the method further involves preserving values from a checkpointed location for the program in the set of physical registers until results from a checkpointed region are committed.

12. The method of claim 11 , wherein committing the checkpointed region involves:

updating the checkpoint map with up-to-date mappings for architectural registers from the retire rename map; and

freeing any physical registers that are no longer mapped to by an architectural register in the checkpoint rename map.

13. The method of claim 12 ,

wherein the processor supports a non-checkpointed mode in which individual program instructions commit immediately after executing; and

wherein the processor allows individual program instructions to commit immediately by mirroring updates to the retire rename map to the checkpoint rename map.

14. The method of claim 10 ,

wherein the method further involves using the plurality of rename maps to facilitate precise exception semantics for the virtual machine.

15. The method of claim 14 , wherein the method further involves executing a subset of the program as interpreted virtual machine instructions after rolling back program execution to the preceding checkpoint.

16. The method of claim 10 ,

wherein additional physical registers in the processor facilitate out-of-order execution;

wherein a first subset of the architectural registers are subject to checkpointing and roll-back; and

wherein a second subset of the architectural registers are not subject to checkpointing and/or roll-back, and instead commit immediately upon the retirement of an associated instruction.

17. The method of claim 10 , wherein rolling back program execution to the preceding checkpoint involves discarding the results of any instructions executed after the preceding checkpoint.

18. A non-transitory computer readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for using register rename maps to facilitate precise exception semantics for a program, wherein the program executes on a processor that supports out-of-order execution, wherein the processor tracks mappings between architectural registers and physical registers for the program using a working rename map, a retire rename map, and a checkpoint rename map, the method comprising:

using the working rename map to map architectural registers associated with a decoded instruction to corresponding physical registers;

using the retire rename map to track and preserve a set of physical registers that are associated with retired instructions;

using the checkpoint rename map to store a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program; and

when the program causes an exception, using the checkpoint rename map to roll back program execution to the preceding checkpoint wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.