High-speed receiver architecture
View Patent ↗A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
1. A multi-channel equalizer comprising:
a feedforward equalizer (FFE) coupled to receive an interleaved signal from a plurality of different channels, the feedforward equalizer capable of applying different equalization coefficients to data bits received from the different channels;
a Viterbi decoder coupled to an output of the feedforward equalizer, the Viterbi decoder determining detected symbols based on a channel model of at least one of the different channels; and
a channel estimator coupled to receive the output of the feedforward equalizer and the output of the Viterbi decoder and produce an error feedback signal to adaptively update the equalization coefficients of the feedforward equalizer based on the error feedback signal, the channel estimator modeling a response of the at least one channel based on a Volterra series model of the at least one channel and providing an input to the Viterbi decoder indicative of the channel model.
2. The multi-channel equalizer of claim 1 wherein the Volterra series model is a weighted sum of input bits, products of input bits, and a constant term.
3. The multi-channel equalizer of claim 2 , wherein the Volterra series model is a weighted sum of a constant, N individual input bits, and all possible products containing two or more of those N input bits.
4. The multi-channel equalizer of claim 2 , wherein the Volterra series model is a weighted sum of a constant, the input bits, and all pair-wise, triple-wise, and quadruple wise products of four input bits.
5. The multi-channel equalizer of claim 2 , wherein the channel estimator forces the constant term to a predetermined value that compensates for baseline wander.
6. The multi-channel equalizer of claim 2 , wherein the channel estimator forces the constant term to zero in the Volterra series model.
7. The multi-channel equalizer of claim 2 , wherein the channel estimator forces a coefficient of a linear term corresponding to a most recently received bit to a predetermined value that fixes a scaling factor for the channel estimator.
8. The multi-channel equalizer of claim 2 , wherein the channel estimator forces a coefficient of a linear term corresponding to a most recently received bit to 1 in the Volterra series model.
9. The multi-channel equalizer of claim 2 , wherein the channel estimator forces a coefficient of an oldest bit to a predetermined value that trains an anticausal response of the channel estimator.
10. The multi-channel equalizer of claim 2 , wherein the channel estimator forces a coefficient of an oldest bit to 1 in the Volterra series model.
11. A method for equalizing an input signal comprising:
receiving a digital interleaved input signal from a plurality of channels;
equalizing the digital input signal using a feedforward equalizer (FFE) by applying different equalization coefficients to input bit from at least two different channels;
decoding the equalized signal using a Viterbi decoder to determine an output signal comprising detected symbols in the equalized digital input signal based on a channel model of at least one of the plurality of channels; and
comparing the equalized signals to the output signal to produce an error signal;
adaptively updating the equalization coefficients of the feedforward equalizer based on the error signal;
modeling a response of the at least one channel based on a Volterra series model of the at least one channel to generate the channel model; and
providing a feedback input to the Viterbi decoder indicative of the channel model.
12. The method of claim 11 , wherein the Volterra series model is a weighted sum of input bits, products of input bits, and a constant term.
13. The method of claim 12 , wherein the Volterra series model is a weighted sum of a constant, N individual input bits, and all possible products containing two or more of those N input bits.
14. The method of claim 12 , wherein the Volterra series model is a weighted sum of a constant, the input bits, and all pair-wise, triple-wise, and quadruple wise products of four input bits.
15. The method of claim 12 , further comprising forcing the constant term to a predetermined value that compensates for baseline wander.
16. The method of claim 12 , further comprising forcing the constant term to zero in the Volterra series model.
17. The method of claim 12 , further comprising forcing a coefficient of a linear term corresponding to a most recently received bit to a predetermined value that fixes a scaling factor for the channel estimator.
18. The method of claim 12 , further comprising forcing a coefficient of a linear term corresponding to a most recently received bit to 1 in the Volterra series model.
19. The method of claim 12 , further comprising, forcing a coefficient of an oldest bit to a predetermined value that train an anticausal response of the channel estimator.
20. The method of claim 12 , further comprising, forcing a coefficient of an oldest bit to 1 in the Volterra series model.