BUFFER WITH REMOTE CASCODE TOPOLOGY
A buffer circuit is described for buffering signals between a circuit element and a load. The buffer includes a main transistor and a cascode transistor, as well as a distribution line for transferring signals over a distance between the circuit element and the load. The buffer is arranged in a remote cascode topology such that the cascode transistor is located substantially adjacent to the load and remote from the main transistor. The distribution line transfers signals over the distance from the main transistor to the cascode transistor. This remote cascode topology makes it possible to significantly reduce the power consumption of the buffer—as compared to conventional buffers—while maintaining the maximum bandwidth possible.
1 . A method of buffering a signal between a circuit element and a load with a cascode buffer, comprising the steps of:
locating a cascode transistor of said cascode buffer substantially adjacent to said load and remote from a main transistor of said cascode buffer; and
transferring signals from said main transistor to said cascode transistor via a distribution line.
2 . The method of claim 1 wherein said step of locating a cascode transistor further comprises connecting a source of said cascode transistor of said buffer to a drain of said main transistor of said buffer via said distribution line.
3 . The method of claim 2 further comprising the step of adding a resistance to a gate of said cascode transistor, wherein a value of said resistance is selected to maximize the bandwidth of said buffer.
4 . The method of claim 3 wherein said buffer comprises a local oscillator (LO) buffer.
5 . The method of claim 4 wherein said LO buffer comprises a differential LO buffer.
6 . The method of claim 4 wherein said load comprises a substantially capacitive load.
7 . The method of claim 4 wherein said load comprises a substantially inductive load.
8 . A transmitter, comprising:
a frequency synthesizer having a local oscillator (LO) that generates an LO-output signal comprising a high-frequency periodic signal;
an up-conversion circuit for up-converting signals to be transmitted by an antenna; and
a buffer circuit for buffering said LO-output signal between said frequency synthesizer and said up-conversion circuit, said buffer circuit including a main transistor, a cascode transistor and a distribution line for transferring signals over a distance;
wherein said cascode transistor of said buffer circuit is located substantially adjacent to said up-conversion circuit and substantially remote from said frequency synthesizer, and wherein said distribution line connects a drain of said main transistor to a source of said cascode transistor.
9 . The transmitter of claim 8 further comprising a predetermined resistance added to a gate of said cascode transistor, said resistance being selected to maximize a bandwidth of said buffer circuit.
10 . The transmitter of claim 9 wherein said transistors of said buffer circuit are formed from CMOS technology.
11 . The transmitter of claim 9 wherein said buffer comprises a differential buffer.
12 . The transmitter of claim 9 wherein said transistors of said buffer are formed from BJT technology.
13 . A communications terminal, comprising:
a frequency synthesizer having a local oscillator (LO) that generates an LO-output signal comprising a high-frequency periodic signal;
a down-conversion circuit for down-converting signals received by an antenna; and
a buffer circuit for buffering said LO-output signal between said frequency synthesizer and said down-conversion circuit, said buffer circuit including a main transistor, a cascode transistor and a distribution line for transferring signals over a distance;
wherein said cascode transistor of said buffer circuit is located substantially adjacent to said down-conversion circuit and substantially remote from said frequency synthesizer, and wherein said distribution line connects a drain of said main transistor to a source of said cascode transistor.
14 . The communications terminal of claim 13 further comprising a predetermined resistance added to a gate of said cascode transistor, said resistance being selected to maximize a bandwidth of said buffer circuit.
15 . The communications terminal of claim 14 wherein said transistors of said buffer circuit are formed from CMOS technology.
16 . The communications terminal of claim 14 wherein said buffer circuit comprises a differential buffer.