IP Library Granted Patent US 7,804,093
Granted Patent B2
US 7,804,093 · App. 12/335,928 · Granted Sep 28, 2010

Thin film transistor array panel and manufacturing method of the same

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Quick Facts
Patent No.
US 7,804,093
App. No.
12/335,928
Granted
Sep 28, 2010
Kind
B2
Abstract

A thin film transistor array panel includes an insulating substrate, a gate line and a data line disposed on the insulating substrate and insulated from and intersecting each other, a thin film transistor connected to the gate line and the data line, a partition disposed corresponding to the gate line and the data line and defining a color filter filling region, a color filter disposed in the filling region, a passivation layer disposed on the color filter and the partition, and a pixel electrode disposed on the passivation layer and connected to the thin film transistor through a contact hole disposed through the passivation layer and the color filter. A plane shape of the color filter filling region is substantially a rectangle.

Claims (24)

1. A thin film transistor array panel comprising:

an insulating substrate;

a gate line and a data line disposed on the insulating substrate, insulated from and intersecting each other;

a thin film transistor connected to the gate line and the data line;

a partition disposed corresponding to the gate line and the data line, and defining a color filter filling region;

a color filter disposed in the filling region;

a passivation layer disposed on the color filter and the partition; and

a pixel electrode disposed on the passivation layer and connected to the thin film transistor through a contact hole disposed through the passivation layer and the color filter,

wherein a plane shape of the color filter filling region is substantially a rectangle.

2. The thin film transistor array panel of claim 1 , wherein

boundaries of the passivation layer and the color filter adjacent to the contact hole are disposed substantially coplanarly.

3. The thin film transistor array panel of claim 1 , wherein

the contact hole is disposed at a position in the filling region.

4. The thin film transistor array panel of claim 1 , wherein

a thickness of the partition and the color filter is more than approximately 0.3 micrometer (μm), the thickness taken substantially perpendicular to the insulating substrate.

5. The thin film transistor array panel of claim 1 , wherein

the partition includes a black pigment.

6. The thin film transistor array panel of claim 1 , wherein

the passivation layer includes a photosensitive organic material.

7. The thin film transistor array panel of claim 1 , wherein

the partition includes an expansion portion disposed in the filling region, and

the contact hole is disposed coinciding with the expansion portion.

8. The thin film transistor array panel of claim 7 , wherein:

boundaries of the passivation layer and the expansion portion defining the contact hole are disposed substantially coplanarly.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: SAMSUNG DISPLAY CO., LTD.
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 060778/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029093/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2008
From: KIM, JANG-SOO; KIM, SANG-SOO; KIM, SHI-YUL; KIM, JANG-SUB
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 021987/0722 →