Self-correcting computer
View Patent ↗The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user.
1. A system comprising:
three or more processors running in lock-step;
a controller adapted to receive signals from the processors and being further adapted to determine a majority value for the received signals and detect errors within the received signals;
a memory module adapted to store a prior state of the processors; and
a scrubbing module adapted to resynchronize the processors, at a predetermined time prior to any detection of errors within the received signals, by reconfiguring elements of the processors to the prior state, the resynchronization being in accordance with the majority value.
2. The system of claim 1 , wherein the predetermined time is selected to be a time interval.
3. The system of claim 1 , wherein the predetermined time is selected to be a number of clock cycles.
4. The system of claim 1 , wherein the predetermined time is selected to be reached during an operating system idle time.
5. The system of claim 1 , wherein the controller is adapted to record an error when signals from one or more processors disagrees with the majority value.
6. The system of claim 5 , wherein the controller is adapted to suspend operation of a processor yielding a signal in disagreement with the majority value.
7. The system of claim 1 , wherein the scrubbing module is adapted to resynchronize the processors by:
a) flushing selected processor state elements for each processor into the memory module; and
b) providing each processor with restoration data from the memory module, said restoration data corresponding to a majority value of each of said selected processor state elements.
8. The system of claim 7 , wherein said state elements include registers.
9. The system of claim 7 , wherein said state elements include cache memory.
10. The system of claim 9 , wherein at least a portion of said cache memory is configured as write-through.
11. The system of claim 1 , wherein the controller includes field-programmable gate arrays (FPGAs).
12. The system of claim 11 , wherein the FPGAs are individually fault-tolerant.
13. The system of claim 1 , wherein the controller includes application-specific integrated circuits (ASICs).
14. The system of claim 1 , wherein each processor is provided with a radiation-mitigating shield.
15. The system of claim 1 , further comprising: a radiation-mitigating shield adapted to shield substantially all components of the computer system.
16. The system of claim 1 , wherein the memory module further comprises:
three or more mirrored memory elements; and
a memory scrub module adapted to detect an error in one or more of said memory elements when an entry at a selected address of said one or more memory elements differs from an entry at said selected address of a majority of said memory elements.
17. The system of claim 16 , wherein said memory scrub module is adapted to test for errors at each read or write to said selected address.
18. The system of claim 16 , wherein said memory scrub module is adapted to test for errors at regular intervals and to reconfigure an entry at an address of one or more of said memory elements when said entry differs from an entry at said address of a majority of said memory elements.
19. The system of claim 1 , wherein the memory module includes error detection and correction logic.
20. The system of claim 19 , wherein the error detection and correction logic includes Reed-Solomon error correction.
21. The system of claim 1 , wherein the predetermined time is selected to be a predetermined interval.
22. The system of claim 1 , wherein predetermined time is selected to be determined as a function of the reliability of the computer system.