Transistor design and layout for performance improvement with strain
View Patent ↗The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis. Subsequently, a uniaxial or biaxial tensile stress 908 is applied to the source to drain channel regions of the N type devices and a uniaxial or biaxial compressive stress 910 is applied to the source to drain channel regions of the P type devices.
1. A semiconductor device comprising:
a semiconductor substrate having a first crystallographic orientation axis and a distinct second crystallographic orientation axis;
a first type of transistor formed in the semiconductor substrate having a channel region aligned in a direction from source to drain along the first crystallographic orientation axis; and
a second type of transistor formed in the semiconductor substrate having a channel region aligned in a direction from source to drain along the second crystallographic orientation axis and rotated in a source to drain direction from the channel region of the first type of transistor by an offset angle, wherein the first type of transistor is p-type and the second type of transistor is n-type and wherein the first crystallographic orientation axis is <110>and the second crystallographic orientation axis is <100>.
2. The device of claim 1 , wherein the channel region of the first type of transistor has improved channel mobility from applied strain along the first crystallographic orientation axis and wherein the channel region of the second type of transistor has improved channel mobility from applied strain along the second crystallographic orientation axis.
3. The device of claim 1 , wherein the first type of transistor is n-type and the second type of transistor is p-type.
4. The device of claim 1 , wherein the offset angle is 45 degrees.
5. The device of claim 1 , wherein an epitaxial layer of silicon-germanium is formed on the channel region of the first type of transistor to apply a compressive strain to the channel region along the <110>crystallographic orientation axis.
6. The device of claim 5 , wherein a layer of carbon doped silicon is formed on the channel region of the second type of transistor to apply a tensile strain to the channel region along the <100>crystallographic orientation axis.
7. A semiconductor device comprising:
a semiconductor substrate having a first and second distinct crystallographic orientation axes;
a first type of lateral transistor formed in the semiconductor substrate having a channel region aligned in a direction from source to drain along the first crystallographic orientation axis; and
a second type of lateral transistor formed in the semiconductor substrate having a channel region aligned in a direction from source to drain along the second crystallographic orientation axis and offset from the first type of transistor by an offset angle, wherein:
the channel region of the first type of lateral transistor has improved channel mobility from applied strain along the first crystallographic orientation axis and wherein the channel region of the second type of lateral transistor has improved channel mobility from applied strain along the second crystallographic orientation axis;
the first type of lateral transistor is p-type and the second type of lateral transistor is n-type; and
the first crystallographic orientation axis is <110>and the second crystallographic orientation axis is <100>.
8. The device of claim 7 , wherein the first type of lateral transistor is n-type and the second type of lateral transistor is p-type.
9. The device of claim 7 , wherein the offset angle is 45 degrees.
10. The device of claim 7 , wherein an epitaxial layer of silicon-germanium is formed on the channel region of the first type of lateral transistor to apply a compressive strain to the channel region along the <110>crystallographic orientation axis.
11. The device of claim 10 , wherein a layer of carbon doped silicon is formed on the channel region of the second type of lateral transistor to apply a tensile strain to the channel region along the <100>crystallographic orientation axis.