System and method for reducing memory requirements for electrical domain compensation of intra-channel nonlinearity in an optical communications system
View Patent ↗A digital filter is provided for processing an electrical input signal to be conveyed through an optical communications system. The processing generates a predistorted electrical signal using a compensation function that substantially mitigates for intra-channel non-linearity imparted to the communications signal by the optical communications system. The digital filter has a memory having a limited size storing a reduced data set used for approximating an original, unreduced data set used to implement the compensation function. The reduced data set is used for the digital filter to apply the compensation function to mitigate the intra-channel non-linearity over longer transmission distances of the optical communications system than would be possible without the use of the reduced data set.
1. A digital filter for processing an electrical input signal to be conveyed through an optical communications system, the processing for generating a predistorted electrical signal using a compensation function that substantially mitigates intra-channel non-linearity imparted to the signal by the optical communications system, the digital filter comprising:
a serial to parallel converter for converting the electrical input signal into a parallel digital signal having a width of at least N bits;
first and second memories connected to receive a respective set of N/2 bits of the parallel digital signal, each memory storing a respective data set computed based on the compensation function and generating at least one output vector comprising a portion of its data set, based on its respective received set of N/2 bits of the parallel digital signal; and
a vector combiner for combining the output vectors generated by the first and second memories to yield the predistorted electrical signal.
2. The digital filter as claimed in claim 1 , wherein the parallel digital signal has a width of greater than N bits, and wherein the respective sets of N/2 bits supplied to each memory are symmetrically disposed about a center of the parallel digital signal.
3. The digital filter as claimed in claim 2 , further comprising:
an adder tree connected to compute a sum over bits of the parallel digital signal lying outside the sets of N/2 bits supplied to each memory; and
a summation block for combining an output of the adder tree with the predistorted electrical signal output from the vector combiner.
4. The digital filter as claimed in claim 1 , wherein the first and second memories are configured to generate a set of three output vectors A(n), X and B(n), where n is an index n=1 . . . N/2, and wherein the vector combiner is configured to calculate the predistorted electrical signal as Y=A(n)xX+B(n).
5. The digital filter as claimed in claim 1 , wherein the first and second memories are configured to generate a set of two output vectors X and B(n), where n is an index n=1 . . . N/2, and wherein the vector combiner is configured to calculate the predistorted electrical signal as Y=X+B(n).
6. A transmitter for transmitting an input signal through an optical communications system, the transmitter comprising:
a digital filter for processing the input signal to generate a predistorted electrical signal using a compensation function that substantially mitigates intra-channel non-linearity imparted to the signal by the optical communications system, the digital filter including:
a serial to parallel converter for converting the electrical input signal into a parallel digital signal having a width of at least N bits;
first and second memories connected to receive a respective set of N/2 bits of the parallel digital signal, each memory storing a respective data set computed based on the compensation function and generating at least one output vector comprising a portion of its data set, based on its respective received set of N/2 bits of the parallel digital signal; and
a vector combiner for combining the output vectors generated by the first and second memories to yield the predistorted electrical signal;
an electrical-to-optical converter for converting the predistorted electrical signal into a corresponding predistorted optical signal for transmission through the optical communications system.
7. The transmitter as claimed in claim 6 , wherein the parallel digital signal has a width of greater than N bits, and wherein the respective sets of N/2 bits supplied to each memory are symmetrically disposed about a center of the parallel digital signal.
8. The transmitter as claimed in claim 7 , further comprising:
an adder tree connected to compute a sum over bits of the parallel digital signal lying outside the sets of N/2bits supplied to each memory; and
a summation block for combining an output of the adder tree with the predistorted electrical signal output from the vector combiner.
9. The transmitter as claimed in claim 6 , wherein the first and second memories are configured to generate a set of three output vectors A(n), X and B(n), where n is an index n=1 . . . N/2, and wherein the vector combiner is configured to calculate the predistorted electrical signal as Y=A(n)xX+B(n).
10. The transmitter as claimed in claim 6 , wherein the first and second memories are configured to generate a set of two output vectors X and B(n), where n is an index n=1 . . . N/2, and wherein the vector combiner is configured to calculate the predistorted electrical signal as Y=X+B(n).
11. A method of processing an electrical input signal to be conveyed through an optical communications system, the processing generating a predistorted electrical signal using a compensation function that substantially mitigates intra-channel non-linearity imparted to the signal by the optical communications system, the method comprising:
converting the electrical input signal into a parallel digital signal having a width of at least N bits;
supplying a respective set of N/2 bits of the parallel digital signal to each one of first and second memories, each memory storing a respective data set computed based on the compensation function and generating at least one output vector comprising a portion of its data set, based on its respective received set of N/2 bits of the parallel digital signal; and
combining the output vectors generated by the first and second memories to yield the predistorted electrical signal.
12. The method as claimed in claim 11 , wherein the parallel digital signal has a width of greater than N bits, and wherein the respective sets of N/2 bits supplied to each memory are symmetrically disposed about a center of the parallel digital signal.
13. The method as claimed in claim 12 , further comprising:
computing a sum over bits of the parallel digital signal lying outside the sets of N/2 bits supplied to each memory; and
combining the computed sum with the predistorted electrical signal.
14. The method as claimed in claim 11 , further comprising steps of:
computing a first data set based on the compensation function, the first data set comprising 2 N/2 vectors, each vector having 2 N/2 elements;
processing the first data set using a compression function to derive at least a second data set and a third data set;
storing the second data set in the first memory; and
storing the third data set in the second memory.
15. The method as claimed in claim 14 , wherein the compression function comprises a Principal Component Analysis.
16. The method as claimed in claim 11 , wherein the first and second memories are configured to generate a set of three output vectors A(n), X and B(n), where n is an index n=1 . . . N/2, and wherein the predistorted electrical signal is calculated as Y=A(n)xX+B(n).
17. The method as claimed in claim 11 , wherein the first and second memories are configured to generate a set of two output vectors X and B(n), where n is an index n=1 . . . N/2, and wherein the predistorted electrical signal is calculated as Y=X+B(n).