IP Library Granted Patent US 8,300,988
Granted Patent B2
US 8,300,988 · App. 12/337,599 · Granted Oct 30, 2012

System for pipelined processing

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Quick Facts
Patent No.
US 8,300,988
App. No.
12/337,599
Granted
Oct 30, 2012
Kind
B2
Abstract

An example embodiment includes a processor module, a pipe analyzer and a central processing unit. The processor module extracts a plurality of components from an input bit stream by extracting predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components. The central processing unit has at least two pipelines for receiving the components derived from the input bit stream. The pipe analyzer is coupled between the processor module and the central processing unit for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis the pipe analyzer.

Claims (13)

1. A system for pipelined processing comprising:

a processor module implementing a method for extracting a plurality of components from an input bit stream by extracting a predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components;

a central processing unit having at least two pipelines for receiving the components of the input bit stream for processing purposes; and

a pipe analyzer coupled between the processor module and the central processing unit implementing a method for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis, the pipe analyzer utilizing a look-up table having a plurality of associated parallel processing code segments.

2. The system as set forth in claim 1 wherein at least one of the processor module and the pipe analyzer comprises hardware.

3. The system as set forth in claim 2 wherein said hardware is a part of said central processing unit.

4. The system as set forth in claim 1 wherein the method of said processor module and the method of said pipe analyzer are implemented in software.

5. The system as set forth in claim 4 wherein said software is executed by a computer system.

6. The system as set forth in claim 5 wherein the computer system includes memory in which program instructions comprising software may be at least temporarily stored.

7. A computer implemented process including code segments stored in digital memory of a computer for managing input data for parallel processing comprising:

code segments for extracting a plurality of components from an input bit stream; and

code segments for analyzing the components of the input bit stream using a look-up table and assigning each component a suitable pipeline for parallel processing;

wherein said look-up table includes a plurality of associated parallel processing code segments.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2017
From: FORTRESS CREDIT CO LLC
To: DBEZ FIRENZE LLC
Reel/Frame 041121/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2017
From: VSTREAM TECHNOLOGIES, LLC
To: FORTRESS CREDIT CO LLC
Reel/Frame 041554/0350 →
SECURITY INTEREST Recorded Apr 4, 2014
From: VSTREAM TECHNOLOGIES LLC
To: FORTRESS CREDIT CO LLC
Reel/Frame 032610/0698 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2013
From: MEDICI PORTFOLIO ACQUISITION LLC
To: VSTREAM TECHNOLOGIES LLC
Reel/Frame 031420/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2013
From: G&H NEVADA-TEK
To: MEDICI PORTFOLIO ACQUISITION LLC
Reel/Frame 031420/0226 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2011
From: NEOSTAR, INC.
To: G&H NEVADA-TEK
Reel/Frame 027172/0558 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2011
From: GOUGH, MICHAEL L.; MINER, PAUL
To: NEOSTAR, INC.
Reel/Frame 027172/0561 →