Gate driving circuit and display apparatus having the same

1. A gate driving circuit comprising stages, the stages being cascaded with each other and each comprising:

a pull-up part which pulls up a gate voltage to an input clock;

a carry part which pulls up a carry voltage to the input clock;

a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part;

a pull-down part receiving a subsequent gate voltage from a subsequent stage to lower the gate voltage to the off-voltage;

a holding part which holds the gate voltage at an off-voltage; and

an inverter for at least one of turning on the holding part and turning off the holding part based on an inverter clock,

wherein a high level of the inverter clock in a given horizontal scanning period (1H) temporally precedes a high level of the input clock by a predetermined time interval in the given horizontal scanning period (1H).

2. The gate driving circuit of claim 1 , wherein the inverter comprises:

a first inverter transistor including an input electrode and a control electrode which receive the inverter clock;

a second inverter transistor including an input electrode which receives the inverter clock, a control electrode connected to the input electrode of the second inverter transistor through a first capacitor and an output electrode connected to an output electrode of the first inverter transistor through a second capacitor and further connected to a control terminal of the holding part;

a third inverter transistor including an input electrode connected to the output electrode of the first inverter transistor, a control electrode connected to an output terminal of the pull-up part and an output electrode which receives the off-voltage; and

a fourth inverter transistor including an input electrode connected to the control terminal of the holding part, a control electrode connected to the output terminal of the pull-up part and an output electrode which receives the off-voltage.

3. The gate driving circuit of claim 2 , wherein the holding part comprises a holding transistor including a control electrode connected to the input electrode of the fourth inverter transistor, an input electrode which receives the off-voltage and an output electrode connected to the output terminal of the pull-up part.

4. The gate driving circuit of claim 1 , wherein the inverter clock comprises:

a first period during which the inverter clock is maintained at a high level; and

a second period during which the inverter clock is maintained at a low level,

wherein a duration of the second period is less than a duration of the first period.

5. The gate driving circuit of claim 4 , wherein the input clock comprises:

a third period during which the input clock is maintained at the high level; and

a fourth period during which the input clock is maintained at the low level, wherein

a duration of the third period is equal to a duration of the fourth period, and

the duration of the first period of the inverter clock is greater than the duration of the third period of the input clock.

6. The gate driving circuit of claim 5 , wherein the duration of the second period of the inverter clock is less than the duration of the fourth period of the input clock.

7. The gate driving circuit of claim 4 , wherein

the inverter clock further comprises a first inverter clock and a second inverter clock,

a phase of the second inverter clock is opposite to a phase of the first inverter clock,

the first inverter clock is input to inverters disposed in odd-numbered stages of the stages, and

the second inverter clock is input to inverters disposed in even-numbered stages of the stages.

8. The gate driving circuit of claim 1 , wherein the pull-up part comprises a pull-up transistor including a control electrode connected to the Q-node, an input electrode which receives the input clock and an output electrode which outputs the gate voltage.

9. The gate driving circuit of claim 8 , wherein the pull-up driving part comprises:

a buffer transistor including a control electrode and an input electrode which receive the previous carry voltage, and an output electrode connected to the Q-node; and

a third capacitor connected between the control electrode of the pull-up transistor and the output electrode of the pull-up transistor.

10. The gate driving circuit of claim 1 , wherein the carry part comprises a carry transistor including a control electrode connected to the Q-node, an input electrode which receives the input clock and an output electrode which outputs the carry voltage.

11. A display apparatus comprising:

a display part which displays an image based on a gate voltage and a data voltage;

a data driving circuit which applies the data voltage to the display part; and

a gate driving circuit comprising stages which sequentially apply the gate voltage to the display part, the stages being cascaded with each other and each of the stages of the gate driving circuit comprising:

a pull-up part which pulls up the gate voltage to an input clock during a given horizontal scanning period (1H);

a carry part which pulls up a carry voltage to the input clock during the given horizontal scanning period (1H);

a pull-down part which receives a subsequent gate voltage from a subsequent stage to lower the gate voltage to an off-voltage;

a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part, and which turns off the pull-up part and the carry part based on the subsequent gate voltage;

a holding part which holds the gate voltage at the off-voltage; and

an inverter for at least one of turning on the holding part and turning off the holding part based on an inverter clock, wherein

a high level of the inverter clock in the given horizontal scanning period (1H) temporally precedes a high level of the input clock by a predetermined time interval in the given horizontal scanning period (1H).

12. The display apparatus of claim 11 , wherein the inverter comprises:

a first inverter transistor including an input electrode and a control electrode which receive the inverter clock;

a second inverter transistor including an input electrode which receives the inverter clock, a control electrode connected to the input electrode of the second inverter transistor through a first capacitor and an output electrode connected to an output electrode of the first inverter transistor through a second capacitor and further connected to a control terminal of the holding part;

a third inverter transistor including an input electrode connected to the output electrode of the first inverter transistor, a control electrode connected to an output terminal of the pull-up part and an output electrode which receives the off-voltage; and

a fourth inverter transistor including an input electrode connected to the control terminal of the holding part, a control electrode connected to the output terminal of the pull-up part and an output electrode which receives the off-voltage.

13. The display apparatus of claim 12 , wherein the inverter clock comprises:

a first period during which the inverter clock is maintained at a high level; and

a second period during which the inverter clock is maintained at a low level,

wherein a duration of the second period is less than a duration of the first period.

14. The display apparatus of claim 13 , wherein

the inverter clock further comprises a first inverter clock and a second inverter clock,

a phase of the second inverter clock is opposite to a phase of the first inverter clock,

the first inverter clock is input to inverters disposed in odd-numbered stages of the stages, and

the second inverter clock is input to inverters disposed in even-numbered stages of the stages.