IP Library › Granted Patent US 8,484,424
Granted Patent B2
US 8,484,424 · App. 12/338,238 · Granted Jul 9, 2013

Storage system, control program and storage system control method

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Quick Facts
Patent No.
US 8,484,424
App. No.
12/338,238
Granted
Jul 9, 2013
Kind
B2
Abstract

There is provided a storage system including one or more LDEVs, one or more processors, a local memory or memories corresponding to the processor or processors, and a shared memory, which is shared by the processors, wherein control information on I/O processing or application processing is stored in the shared memory, and the processor caches a part of the control information in different storage areas on a type-by-type basis in the local memory or memories corresponding to the processor or processors in referring to the control information stored in the shared memory.

Claims (39)

1. A storage system, comprising:

at least a logical volume storing data from a host computer;

a plurality of processor packages, each of which includes at least one processor and a local memory; and

a shared memory shared by the processors, which stores control information comprising at least a first type and a second type of control information for processing,

wherein:

each of the local memories is divided into a plurality of areas, one of the areas being dedicated for the first type of control information; and

each of the processors is configured to put a part of the first type of control information in the one of the areas of the local memory in the processor package where the processor is included.

2. The storage system according to claim 1 , wherein:

the first of control information is read independently of the area in the logical volume which is accessed by the host computer, and

the second of control information is read dependently of the area in the logical volume which is accessed by the host computer.

3. The storage system according to claim 1 , wherein:

another one of the areas is dedicated for the second type of control information;

each of the processors is configured to put a part of the second type of control information in the another one of the areas of the local memory in the processor package where the processor is included.

4. The storage system according to claim 3 , wherein:

the first type of control information is read independently of the area in the logical volume which is accessed by the host computer, and

the second type of control information is read dependently of the area in the logical volume which is accessed by the host computer.

5. The storage system according to claim 1 , wherein the processor determines whether the control information is to be put in the local memory or not by referring to control information stored in the shared memory.

6. The storage system according to claim 5 , wherein, if the configuration of the storage system is changed, the processors change the settings of the storage areas in accordance with the changed configuration.

7. The storage system according to claim 6 , wherein the processors allocate the storage areas in accordance with the number of volumes on which I/O processing or processing relating to a storage application is performed with reference to the corresponding control information in changing the settings of the storage areas.

8. The storage system according to claim 6 , wherein the processors allocate the storage areas for the number of all volumes if one or more volumes exist on which I/O processing or processing relating to a storage application is performed with reference to the corresponding first type of control information in changing the settings of the storage areas.

9. The storage system according to claim 1 , further comprising:

a management terminal, wherein the status of the storage area for each of the processors is displayed on the management terminal, and the setting of the storage area or each of the storage areas is changed on the basis of the data input from the management terminal.

10. The storage system according to claim 9 , wherein the status of the storage area for each of the processors displayed in the management terminal includes a cache hit probability in the local memory.

11. The storage system according to claim 1 , wherein the processors updating the control information stored in the shared memory notify the update of the control information to the other processors.

12. The storage system according to claim 11 , wherein each of the processors having received the notification of the update of the control information from the other processors invalidates the update if the control information to be updated is cached in the corresponding local memory.

13. The storage system according to claim 11 , wherein the processors updating the control information stored in the shared memory do not notify the update of the control information to the other processors if the control information to be updated is the control information which has not been cached by any of the other processors in the corresponding local memories.

14. The storage system according to claim 13 , wherein the control information which has not been cached by any of the other processors in the corresponding local memories includes the control information accessible only by the processor which is responsible for the volume on which I/O processing or processing relating to a storage application is performed with reference to the corresponding control information.

15. A method for controlling a storage system including at least a logical volume storing data from a host computer, a plurality of processor packages, each of which includes at least one processor and a local memory; and a shared memory shared by the processors, which stores control information comprising at least a first type and a second type of control information for processing, said method comprising:

dividing each of the local memories into a plurality of areas, one of the areas being dedicated for the first type of control information; and

putting, for each of the processors, a part of the first type of control information in the one of the areas of the local memory in the processor package where the processor is included.

16. The method according to claim 15 , wherein:

the first of control information is read independently of the area in the logical volume which is accessed by the host computer, and

the second of control information is read dependently of the area in the logical volume which is accessed by the host computer.

17. The method according to claim 15 , wherein:

another one of the areas is dedicated for the second type of control information; and

said method further comprising, putting, for each of the processors, a part of the second type of control information in the another one of the local memory in the processor package where the processor is included.

18. The method according to claim 17 , wherein:

the first of control information is read independently of the area in the logical volume which is accessed by the host computer, and

the second of control information is read dependently of the area in the logical volume which is accessed by the host computer.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2008
From: ITO, SHINTARO; SHIMOZONO, NORIO
To: HITACHI, LTD.
Reel/Frame 022002/0678 →