An RF squarer circuit comprises a first RF multiplier and a first variable gain transimpedance amplifier (TIA). The first RF multiplier receives an RF input signal RFIN and provides a first output current. The first TIA receives the first output current as an input. The first TIA provides an output voltage VOUT.
1. An RF squarer circuit, comprising:
a first RF multiplier, the first RF multiplier receiving an RF input signal RFIN and providing a first output current; and
a first variable gain transimpedance amplifier (TIA), the first TIA receiving as an input, the first output current; wherein the first TIA provides an output voltage VOUT;
a second RE multiplier;
a second variable transimpedance amplifier (TIA); and
a voltage regulator; wherein the second RF multiplier receives a known input DC voltage (DCIN) and feeds a second output current to the second TIA, and the second TIA provides a second output voltage to the voltage regulator, and the voltage regulator providing an output regulator voltage (VREG) to the first and second RF multipliers.
2. The RE squarer circuit of claim 1 , wherein the VOUT behaves in accordance with the equation:
(
A
·
Cos
(
ω
)
)
2
=
A
2
2
(
1
+
Cos
(
2
ω
)
)
,
where A is an amplitude of REIN and ω is an angular frequency of RFIN.
3. The RF squarer circuit of claim 1 , wherein the first RF multiplier is a current-mode RE multiplier.
4. The RF squarer circuit of claim 3 , wherein the first RF multiplier includes a Gilbert Cell with a degeneration transistor in parallel with a signal transistor.
5. The RF squarer circuit of claim 1 , wherein the first variable gain transimpedance amplifier (TIA) includes a two-stage amplifier.
6. The RF squarer circuit of claim 5 , wherein the two-stage amplifier includes a cascade of two transconductance amplifiers.
7. The RF squarer circuit of claim 1 , wherein the first RF multiplier and the first TIA for a main path and the second RF multiplier, second TIA, and voltage regular form a replica path.
8. The RF squarer circuit of claim 1 , wherein the first and second RF multipliers are current-mode RF multiplier; and
wherein the first variable gain transimpedance amplifier (TIA) includes a two-stage amplifier, the two-stage amplifier including a cascade of two trans conductance amplifiers.
9. The RF squarer circuit of claim 1 , wherein the first and second RF multipliers each include a Gilbert Cell with a degeneration transistor in parallel with a signal transistor; and
wherein DCIN is relatively constant over process, temperature and voltage (PVT) and VREG controls a gain of each of the RF multipliers to be relatively constant over PVT.
10. The RF squarer circuit of claim 1 , wherein:
the VOUT behaves in accordance with the equation:
(
A
·
Cos
(
ω
)
)
2
=
A
2
2
(
1
+
Cos
(
2
ω
)
)
,
where A is an amplitude of RFIN and ω is an angular frequency of RFIN.
11. An RF squarer circuit, comprising:
a main path for receiving an input RF signal (RFIN) and providing an output voltage (VOUT) representative of an amplitude of RFIN squared;
a replica path for providing a control voltage (VREG) to control a gain of the main path, wherein the replica path receives a known input DC voltage (DCIN) that is relatively constant over process, temperature and voltage (PVT) and VREG provides for stable control of the gain of the main path over PVT.
12. The RF squarer circuit of claim 11 , wherein:
the main path comprises a first current-mode RF multiplier and a first transimpedance amplifier, the first current-mode RF multiplier receives RFIN and feeds the first TIA with a first output current and the first output TIA provides VOUT.
13. The RF squarer circuit of claim 11 , wherein:
the replica path comprises a second current-mode RF multiplier, a second transimpedance amplifier (TIA) and a voltage regulator, the second current-mode RF multiplier receiving DCIN and feeding a second output current to the second TIA, and the second TIA provides a second output voltage, and the voltage regulator compares the second output voltage with DCIN and provides VREG responsive to the second output voltage and DCIN.
14. The RF squarer circuit of claim 12 , wherein:
the main path comprises a first current-mode RF multiplier and a first transimpedance amplifier, the first current-mode RF multiplier receives RFIN and feeds the first TIA with a first output current and the first output TIA provides VOUT; and
wherein the replica path comprises a second current-mode RF multiplier, a second transimpedance amplifier (TIA) and a voltage regulator, the second current-mode RF multiplier receiving DCIN and feeding a second output current to the second TIA, and the second TIA provides a second output voltage, and the voltage regulator compares the second output voltage with DCIN and provides VREG responsive to the second output voltage and DCIN.
15. The RF squarer circuit of claim 14 , wherein the first transimpedance amplifier (TIA) includes a two-stage amplifier, the two-stage amplifier including a cascade of two transconductance amplifiers, the first and second RF multipliers each include a Gilbert Cell with a degeneration transistor in parallel with a signal transistor.
16. A method of squaring an RF input signal, comprising:
multiplying the RF input signal in a first current-mode RF multiplier;
feeding a first output current from the current-mode RF multiplier to a first two-stage transimpedance amplifier (TIA);
amplifying the first output current from the current-mode RF multiplier in the first two-stage TIA and providing an output voltage VOUT; wherein VOUT is representative of a square of an amplitude of the RF input signal;
controlling a gain of the first current-mode RF multiplier in a replica, wherein controlling the gain of the first current-mode RF multiplier in a replica path comprises:
providing a known input DC voltage in (DCIN), wherein DCIN is relatively constant over process, temperature and voltage (PVC);
multiplying DCIN in a second current-mode RF multiplier and providing a second output current to a second transimpedance voltage amplifier (TIA);
comparing a second output voltage of the second TIA with DCIN at a voltage regulator;
providing an output regulation voltage (VREG); and
feeding VREG to the first current-mode RF multiplier to control the gain of the first current-mode RF multiplier.
17. The method of claim 16 , wherein the first current-mode RF multiplier includes a Gilbert Cell with a degeneration transistor in parallel with a signal transistor.
18. The method of claim 16 , wherein the first two-stage TIA includes a cascade of two transconductance amplifiers.
19. The method of claim 16 , wherein the first current-mode RF multiplier includes a Gilbert Cell with a degeneration transistor in parallel with a signal transistor.
20. The method of claim 16 , wherein the first two-stage TIA includes a cascade of two transconductance amplifiers and the first current-mode RF multiplier includes a Gilbert Cell with a degeneration transistor in parallel with a signal transistor.