Scalable cost function generator and method thereof

1. A cost function generator circuit, comprising:

a plurality of memory terms each receiving one or more input signals, and each providing inphase and quadrature output currents corresponding to a delay relative to the input signals, wherein the delay of each memory term is different from the delays of the other memory terms, wherein the inphase output currents of the memory terms are summed to provide a combined inphase output current, and wherein the quadrature output currents of the memory terms are summed to provide a combined quadrature output current; and

transimpedance amplifier means receiving the combined inphase output current and the combined quadrature output current to provide an inphase output voltage and a quadrature output voltage.

2. A cost function generator circuit as in claim 1 , wherein each memory term comprises:

one or more delay elements each providing a programmable delay, the delay elements implementing the corresponding delay of the memory term;

a first plurality of multipliers receiving the delayed input signals to generate a plurality of harmonics of the delayed input signals;

a plurality of filters that attenuate dc offsets and high frequency components from the harmonics;

a plurality of digital-to-analog converters each converting a digital value into an analog value; and

a second plurality of multipliers each multiplying a selected one of the analog value with a corresponding one of the harmonics to provide a product, wherein a first group of selected products are summed to provide the inphase output current of the memory term, and a second group of selected products are summed to provide the quadrature output current of the memory term.

3. A cost function generator as in claim 2 , wherein each of the second plurality of multipliers and a corresponding one of the digital analog converters are implemented by a combined digital-to-analog converter and multiplier.

4. A cost function generator circuit as in claim 3 , wherein the combined digital-to-analog converter and multiplier comprises:

first and second current sources providing first and second load currents;

a first stage receiving the first and second load currents, the first stage comprising a first 2-quadrant analog multiplier and a second 2-quadrant analog multiplier, the first stage receiving the corresponding harmonic; and

a second stage comprising a plurality of 2-quadrant analog multipliers each connected to the first 2-quadrant analog multiplier of the first stage and the second 2-quadrant multiplier of the second stage to form a 4-quadrant analog multiplier, each 2-quadrant analog multiplier of the second stage receiving a decoded bit of a corresponding digital value.

5. A cost function generator as in claim 4 , wherein the first and second load currents are each compensated for variations in PVT.

6. A cost function generator as in claim 2 , wherein each of the first and second pluralities of multipliers has an individually programmable gain.

7. A cost function generator as in claim 2 , wherein selected ones of the filters are each coupled to a selected one of the first plurality of analog multipliers, such that each selected filter attenuates the high frequency components by an input parasitic impedance of the coupled analog multiplier.

8. A cost function generator as in claim 2 , wherein the delay elements each comprise a passive circuit including at least one pole.

9. A cost function generator as in claim 1 , wherein the transimpedance amplifier means comprises a first transimpedance amplifier and a second transimpedance amplifier.

10. A method for generating a cost function, comprising:

in a plurality of memory terms each receiving one or more input signals, providing from each memory term inphase and quadrature output currents corresponding to a delay relative to the input signals, wherein the inphase output currents of the memory terms are summed to provide a combined inphase output current, and wherein the quadrature output currents of the memory terms are summed to provide a combined quadrature output current; and

using transimpedance amplifier means, which receives the combined inphase output current and the combined quadrature output current, providing an inphase output voltage and a quadrature output voltage.

11. A method as in claim 10 , further comprising carrying out in each memory term:

in one or more delay elements, providing a programmable delay, the delay elements implementing the corresponding delay of the memory term;

in each of a first plurality of multipliers receiving the delayed input signals, generating a plurality of harmonics of the delayed input signals;

in each of a plurality of filters, attenuating dc offsets and high frequency components from the harmonics;

in each of a plurality of digital-to-analog converters, converting a digital value into an analog value; and

in each of a second plurality of multipliers, multiplying a selected one of the analog value with a corresponding one of the harmonics to provide a product, wherein a first group of selected products are summed to provide the inphase output current of the memory term, and a second group of selected products are summed to provide the quadrature output current of the memory term.

12. A method as in claim 11 , wherein each of the second plurality of multipliers and a corresponding one of the digital analog converters are implemented by a combined digital-to-analog converter and multiplier.

13. A method as in claim 12 , further comprising, in the combined digital-to-analog converter and multiplier:

providing first and second load currents in first and second current sources;

providing a first stage receiving the first and second load currents, the first stage comprising a first 2-quadrant analog multiplier and a second 2-quadrant analog multiplier, the first stage receiving the corresponding harmonic; and

providing a second stage comprising a plurality of 2-quadrant analog multipliers each connected to the first 2-quadrant analog multiplier of the first stage and the second 2-quadrant multiplier of the second stage to form a 4-quadrant analog multiplier, each 2-quadrant analog multiplier of the second stage receiving a decoded bit of a corresponding digital value.

14. A method as in claim 13 , wherein the first and second load currents are each compensated for variations in PVT.

15. A method as in claim 11 , wherein each of the first and second pluralities of multipliers has an individually programmable gain.

16. A method as in claim 11 , wherein selected ones of the filters are each coupled to a selected one of the first plurality of analog multipliers, such that each selected filter attenuates the high frequency components by an input parasitic impedance of the coupled analog multiplier.

17. A method as in claim 11 , wherein the delay elements each comprise a passive circuit including at least one pole.

18. A method as in claim 10 , wherein the transimpedance amplifier means comprises a first transimpedance amplifier and a second transimpedance amplifier.