Clock driver circuit
View Patent ↗Clock driver circuit having upper and lower transistors 1 and upper and lower transistors 2 . Voltage node 1 coupled to electrodes of upper transistor 1 and upper transistor 2 . Voltage node 2 coupled to electrodes of lower transistor 1 and lower transistor 2 . Coupling transistor 1 couples another electrode of upper transistor 1 to another electrode of lower transistor 2 . Coupling transistor 2 couples another electrode of upper transistor 2 to another electrode of lower transistor 1 . Two series 1 capacitors couple the another electrode of upper transistor 1 to the another electrode of lower transistor 1 . Two series 2 capacitors couple the another electrode of upper transistor 2 to the another electrode of lower transistor 2 . Node intermediate the two series 2 capacitors provides in-phase clock output. Node intermediate the two series 1 capacitors provides anti-phase clock output. In-phase clock input is coupled to control inputs of upper transistor 1 , coupling transistor 1 and lower transistor 1 . Anti-phase clock input is coupled to control inputs of upper transistor 2 , coupling transistor 2 and lower transistor 2 .
1. A clock driver circuit comprising:
a first upper transistor and a first lower transistor providing a first set of complementary transistors;
a second upper transistor and a second lower transistor providing a second set of complementary transistors;
a first voltage supply node coupled to both an electrode of the first upper transistor and an electrode of the second upper transistor;
a second voltage supply node coupled to both an electrode of the first lower transistor and an electrode of the second lower transistor;
a first coupling transistor selectively coupling another electrode of the first upper transistor to another electrode of the second lower transistor;
a second coupling transistor selectively coupling another electrode of the second upper transistor to another electrode of the first lower transistor;
two first series connected capacitors coupling the another electrode of the first upper transistor to the another electrode of the first lower transistor;
two second identical series connected capacitors coupling the another electrode of the second upper transistor to the another electrode of the second lower transistor;
an in-phase clock signal output provided by a node intermediate the two second series connected capacitors;
an anti-phase clock signal output provided by a node intermediate the two first series connected capacitors;
an in-phase clock signal input coupled to control inputs of the first upper transistor, the first coupling transistor and the first lower transistor; and
an anti-phase clock signal input coupled to control inputs of the second upper transistor, the second coupling transistor and the second lower transistor.
2. A clock driver circuit as claimed in claim 1 , wherein the upper first transistor and upper second transistor are P-type field effect transistors and wherein the lower first transistor and lower second transistor are N-type field effect transistors.
3. A clock driver circuit, as claimed in claim 2 , wherein the first coupling transistor and the second coupling transistor are N-type field effect transistors.
4. A clock driver circuit, as claimed in claim 3 , wherein the first coupling transistor and the second coupling transistor are NPN bipolar transistors.
5. A clock driver circuit, as claimed in claim 1 , wherein the upper first transistor and upper second transistor are PNP bipolar transistors, and wherein the lower first transistor and lower second transistor are NPN bipolar transistors.
6. A clock driver circuit, as claimed in claim 1 , wherein the two first series connected capacitors and the two second series connected capacitors all have identical capacitance values.
7. A clock driver circuit, as claimed in claim 1 , wherein the first voltage supply node is coupled to a positive power supply potential and the second voltage supply node is coupled to a reference potential relative to the positive power supply.
8. A clock driver circuit, as claimed in claim 7 , wherein in operation a first clock signal is applied to the in-phase clock signal input and second clock signal that is anti-phase to the first clock signal is applied to the anti-phase clock signal input.
9. A clock driver circuit, as claimed in claim 7 , wherein the two first series connected capacitors and the two second series connected capacitors all have identical capacitance values and the two first series connected capacitors include a lower first capacitor coupled to the another electrode of the first lower transistor and an upper first capacitor coupled to the another electrode of the first upper transistor, and wherein in operation a charge on the lower first capacitor ranges from the reference potential to half the positive power supply potential and the charge on the upper first capacitor ranges from to half the positive power supply potential to the positive power supply potential.
10. A clock driver circuit, as claimed in claim 9 , wherein in operation a charge on the lower second capacitor ranges from the reference potential to half the positive power supply potential and the charge on the upper second capacitor ranges from to half the positive power supply potential to the positive power supply potential.
11. A clock driver circuit, as claimed in claim 1 , wherein the first upper transistor and first lower transistor are configured and biased to operate in a class AB operation.
12. A clock driver circuit, as claimed in claim 1 , wherein the second upper transistor and first lower transistor are configured and biased to operate in a class AB operation.