Semiconductor integrated circuit
View Patent ↗During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
1. A semiconductor integrated circuit operable with a system clock signal, the semiconductor integrated circuit comprising:
at least two logic circuits which transmit a data signal sequentially and are inputted the system clock signal; and
a control circuit which determines an optimal portion to stop the operation between the at least two logic circuits based on the system clock signal, wherein
the control circuit determines an optimal portion to start the operation between the at least two logic circuits based on the system clock signal during a phase fine-tuning period for the system clock signal.
2. The semiconductor integrated circuit according to claim 1 , wherein
the control circuit determines an optimal portion to stop the operation and to start the operation between the at least two logic circuits based on the system clock signal during a phase fine-tuning period for the system clock signal.