Semiconductor device and photomask
View Patent ↗Shared contact holes SC 1 and SC 2 reach both gate electrode layers GE 1 and GE 2 and a drain region PIR. In a planar view, a sidewall E 2 of gate electrode layers GE 1 and GE 2 is shifted toward a side of a sidewall E 4 from a virtual extended line E 1 a of the sidewall E 1 . In a planar view, a center line of a line width D 1 in a portion that shared contact holes SC 1 and SC 2 of gate electrode layers GE 1 and GE 2 reach is located while shifted with respect to a center line of a line width D 2 in a portion located on channel formation regions CHN 1 and CHN 2 of gate electrode layers GE 1 and GE 2 . Therefore, a semiconductor device and a photomask that can suppress an opening defect of the shared contact hole are obtained.
1. A semiconductor device including a first p-type MISFET, a first n-type MISFET, a second p-type MISFET, and a second n-type MISFET, comprising:
a semiconductor substrate having a main surface;
a first p-type impurity region formed in said main surface;
a first n-type impurity region formed in said main surface;
a second p-type impurity region formed in said main surface;
a second n-type impurity region formed in said main surface;
a first gate electrode formed over said first p-type impurity region and said first n-type impurity region;
a second gate electrode formed over said second p-type impurity region and said second n-type impurity region; and
an insulator film formed over said first p-type impurity region, said first n-type impurity region, said second p-type impurity region, said second n-type impurity region, said first gate electrode, and said second gate electrode,
wherein said first p-type MISFET includes said first p-type impurity region and said first gate electrode,
wherein said first n-type MISFET includes said first n-type impurity region and said first gate electrode,
wherein said second p-type MISFET includes said second p-type impurity region and said second gate electrode,
wherein said second n-type MISFET includes said second n-type impurity region and said second gate electrode,
wherein said insulator film has a shared contact hole reaching both said first gate electrode and said second p-type impurity region,
wherein said first gate electrode includes first, second, third, and fourth sidewalls, said first and third sidewalls being located opposite to each other, said second and fourth sidewalls being located opposite to each other,
wherein, in a planar view, said second sidewall in a portion that said shared contact hole of said first gate electrode reaches is shifted toward sides of said third and fourth sidewalls from a virtual extended line of said first sidewall in portions located on said channel formation regions of said first p-type MISFET and said first n-type MISFET, and
wherein, in a planar view, a center line of a line width in the portion that said shared contact hole of said first gate electrode reaches is located while shifted with respect to a center line of a line width in the portion located on said channel formation regions of said first p-type MISFET and said first n-type MISFET.
2. The semiconductor device according to claim 1 , wherein said fourth sidewall of said first gate electrode in the portion that said shared contact hole reaches is located on a straight line identical to that of said third sidewall of said first gate electrode on said channel formation regions of said first P-type MISFET and said first n-type MISFET.
3. The semiconductor device according to claim 1 , wherein said fourth sidewall of said first gate electrode in the portion that said shared contact hole reaches is located on a straight line different from that of said third sidewall of said first gate electrode on said channel formation regions of said first p-type MISFET and said first n-type MISFET.
4. The semiconductor device according to claim 1 , wherein, in a planar view, said second sidewall of said first gate electrode in the portion that said shared contact hole reaches is parallel to said first sidewall of said first gate electrode on said channel formation regions of said first p-type MISFET and said first n-type MISFET.
5. The semiconductor device according to claim 1 , wherein, in a planar view, said second sidewall of said first gate electrode in the portion that said shared contact hole reaches is inclined with respect to said first sidewall of said first gate electrode on said channel formation regions of said first p-type MISFET and said first n-type MISFET.
6. The semiconductor device according to claim 1 , wherein first and second memory cells each of which includes said first p-type MISFET, said first n-type MISFET, said second p-type MISFET, and said second n-type MISFET are disposed adjacent to each other such that said third and fourth sidewalls of said first gate electrode of said first memory cell and said third and fourth sidewalls of said first gate electrode of said second memory cell face each other in a planar view, and
a spacing between said first sidewall in the portion located on said channel formation regions of said first p-type MISFET and said first n-type MISFET of said first memory cell and said first sidewall in the portion located on said channel formation regions of said first p-type MISFET and said first n-type MISFET of said second memory cell is larger than a spacing between said second sidewall in the portion that said shared contact hole of said first gate electrode of said first memory cell reaches and said second sidewall in the portion that said shared contact hole of said first gate electrode of said second memory cell reaches.
7. The semiconductor device according to claim 1 , wherein said first p-type MISFET, said first n-type MISFET, said second p-type MISFET, and said second n-type MISFET constitute a content addressable memory.
8. A semiconductor device including a first p-type MISFET, a first n-type MISFET, a second-type MISFET, and a second n-type MISFET, comprising:
a semiconductor substrate having a main surface;
a first p-type impurity region formed in said main surface;
a first n-type impurity region formed in said main surface;
a second p-type impurity region formed in said main surface;
a second n-type impurity region formed in said main surface;
a first gate electrode formed over said first p-type impurity region and said first n-type impurity region;
a second gate electrode formed over said second p-type impurity region and said second n-type impurity region; and
an insulator film formed over said first p-type impurity region, said first n-type impurity region, said second p-type impurity region, said second n-type impurity region, said first gate electrode, and said second gate electrode,
wherein said first gate electrode includes a first portion and a second portion,
wherein a width of said first portion is smaller than a width of said second portion,
wherein said second gate electrode includes a third portion and a fourth portion,
wherein a width of said third portion is smaller than a width of said fourth portion,
wherein said first p-type MISFET includes said first p-type impurity region and said second portion of said first gate electrode,
wherein said first n-type MISFET includes said first n-type impurity region and said second portion of said first gate electrode,
wherein said second p-type MISFET includes said second p-type impurity region and said fourth portion of said second gate electrode,
wherein said second n-type MISFET includes said second n-type impurity region and said fourth portion of said second gate electrode,
wherein said insulator film has a first shared contact hole reaching both said first portion of said first gate electrode and said second p-type impurity region, and
wherein said insulator film has a second shared contact hole reaching both said third portion of said second gate electrode and said first p-type impurity region.
9. The semiconductor device according to claim 8 , wherein said first p-type MISFET, said first n-type MISFET, said second p-type MISFET, and said second n-type MISFET constitute an SRAM.
10. The semiconductor device according to claim 9 , wherein said SRAM further includes a third n-type MISFET and a fourth n-type MISFET,
wherein said third n-type MISFET includes said first n-type impurity region and a third gate electrode, and
wherein said fourth n-type MISFET includes said second n-type impurity region and a fourth gate electrode.