3D chip arrangement including memory manager
Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
1. A chip arrangement comprising:
a plurality of dies, wherein at least some of said dies are stacked face-to-face on top of each other and connected via sockets arranged on the respective faces in predefined patterns, wherein the sockets collectively form a bus that runs through all of the stacked dies;
said dies comprising
at least one memory die comprising at least one memory module, and
at least one logic die comprising at least one subsystem;
said chip arrangement further including a memory management unit connected to said at least one memory die and said at least one logic die, wherein said memory management unit is adapted for managing memory accesses from said at least one subsystem to said at least one memory module via the bus.
2. The chip arrangement of claim 1 , wherein at least some of said dies are connected to each other via silicon-through-vias.
3. The chip arrangement of claim 1 , wherein at least one of said at least one logic dies is arranged on a base substrate.
4. The chip arrangement of claim 3 , wherein at least one memory die is stacked on top of said at least one logic die.
5. The chip arrangement of claim 1 , wherein at least one of said logic dies is stacked on top of said at least one memory die.
6. The chip arrangement of claim 1 , comprising at least two memory modules, and further comprising a router connected to at least two of said memory modules, said router being adapted for routing data traffic to and from said at least two memory modules.
7. The chip arrangement of claim 6 , wherein said router is arranged in one of said at least one memory dies.
8. The chip arrangement of claim 1 , wherein said memory management unit is implemented in at least one separate die.
9. The chip arrangement of claim 8 , wherein said memory management unit is stacked between said at least one logic die and said at least one memory die.
10. The chip arrangement of claim 1 , wherein said memory management unit is included in one of said at least one logic dies.
11. A method, comprising:
allocating a first memory region to a first and second subsystem by a memory management unit, wherein said first and second subsystems are part of a respective first and second logic die and said memory region is part of a first memory die both included in a chip arrangement comprising at least the first memory die and one or more of the first and second logic dies stacked face-to-face with each other;
generating, by said memory management unit, a region code associated with said allocated memory region;
storing said region code in connection with an address of said memory region; and
defining said first and second subsystem as respective first and second owners for said memory region by storing unique subsystem identifiers together with said region code in a parameter table at said memory management unit.
12. The method of claim 11 , further comprising transmitting parameters related to said memory region between said subsystem and said memory management unit via a logical memory interface.
13. The method of claim 11 , further comprising transmitting parameters related to said memory region from said first subsystem to a second subsystem via a logical control interface.
14. The method of claim 13 , wherein said logical control interface is provided via a face-to-face connection between said logic die and said memory die.
15. The method of claim 11 , further comprising transferring ownership of said memory region to a third subsystem by changing said stored subsystem identifier at said parameter table.
16. The method of claim 11 , further comprising providing at least one additional local memory management unit on at least one of said memory dies.
17. The method of claim 16 , wherein said step of allocating a memory region further comprises said local memory management unit forwarding a request for memory allocation from said subsystem to said memory management unit.
18. The method of claim 17 , wherein said memory allocation request includes a unique router identifier of a router element associated with said requesting subsystem.
19. The method of claim 16 , further comprising transmitting an allocation acknowledgement from said memory management to said local memory management unit.
20. The method of claim 19 , wherein said allocation acknowledgement includes a unique router identifier of a router element connected to said allocated memory region.
21. The method of claim 20 , wherein said allocation acknowledgement includes at least one of the following parameters: a port number for said router element, a physical memory address of said memory region, a region code of said allocated memory region.
22. The method of claim 16 , further comprising said local memory management unit translating a physical memory address received from said memory management unit into a local memory address specific to said subsystem.