Insulated gate bipolar transistor and method of fabricating the same
View Patent ↗According to embodiments, an insulated gate bipolar transistor (IGBT) may include a first conductive type collector ion implantation area, formed within a substrate, second conductive type first buffer layers, formed over the collector ion implantation area and each including a first segment buffer layer and a second segment buffer layer, a first conductive type poly layer formed from a surface of the substrate to the collector ion implantation area, the first conductive type poly layer having a contact structure, a second buffer layer of the second conductive type, formed in the substrate area next to the first conductive type poly layer. According to embodiments, a segment buffer layer may have different concentrations according areas. Accordingly, amounts of hole currents injected through the buffer layers may differ according to areas.
1. A device comprising:
a collector ion implantation area of a first conductive type, formed within a substrate;
a first buffer layer of a second conductive type, formed over the collector ion implantation area, the first buffer layer including a first segment buffer layer and a second segment buffer layer;
a first conductive type poly layer formed from a surface of the substrate to the collector ion implantation area, the first conductive type poly layer having a contact structure; and
a second buffer layer of the second conductive type, formed in the substrate adjacent to the first conductive type poly layer.
2. The device of claim 1 , wherein the first segment buffer layer has a different concentration of ion implantation than the second segment buffer layer.
3. The device of claim 1 , further comprising:
a base area of the first conductive type, formed over the first buffer layer;
a gate formed over the substrate on one side of the base area; and
an emitter ion implantation area of the second conductive type, formed within the base area.
4. The device of claim 3 , further comprising:
an insulating layer formed over the substrate to expose a portion the substrate between the gate and the first conductive type poly layer;
an emitter electrode electrically connected to the emitter ion implantation area; and
a collector electrode electrically connected to the first conductive type poly layer.
5. The device of claim 3 , further comprising a first ion implantation area of the first conductive type, formed on one side of the emitter ion implantation area.
6. The device of claim 5 , further comprising a second ion implantation area of the first conductive type, formed below the first ion implantation area and below at least a portion of the base area.
7. The device of claim 6 , wherein the first buffer layer comprises:
the first segment buffer layer formed at a location vertically corresponding to the second ion implantation area; and
the second segment buffer layer formed adjacent to the first segment buffer layer.
8. The device of claim 7 , wherein the first segment buffer layer has a concentration of ion implantation lower than that of the second segment buffer layer.
9. The device of claim 1 , wherein the first conductive type comprises a P type and wherein the second conductive type comprises an N type.