IP Library Granted Patent US 8,193,455
Granted Patent B2
US 8,193,455 · App. 12/345,760 · Granted Jun 5, 2012

Graphene electronics fabrication

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Quick Facts
Patent No.
US 8,193,455
App. No.
12/345,760
Granted
Jun 5, 2012
Kind
B2
Abstract

An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact.

Claims (12)

1. A circuit structure comprising:

a plurality of layers of graphene formed one on another; and

first and second electrical contacts, both of the first and second electrical contacts being electrically connected with a single graphene layer of the plurality of layers of graphene, wherein at least a portion of the plurality of graphene layers have first and second edges that define first and second sides, and wherein the single layer of graphene extends beyond the first and second sides.

2. The circuit structure as in claim 1 wherein the single graphene layer is at the top of the plurality of graphene layers.

3. The circuit structure as in claim 1 wherein the single graphene layer is at the bottom of the plurality of graphene layers.

4. The circuit structure as in claim 1 wherein the single graphene layer within the plurality of graphene layers is sandwiched between adjacent graphene layers.

5. The circuit structure as in claim 1 wherein the plurality of graphene layers includes at least three layers of graphene.

6. The circuit structure as in claim 1 wherein the plurality of graphene layers is formed on a substrate.

7. The circuit structure as in claim 1 wherein the plurality of graphene layers is formed on a Si substrate.

8. The circuit structure as in claim 1 wherein the single graphene layer makes contact with the first and second electrical contacts in a region beyond the first and second sides.

9. The circuit structure as in claim 1 further comprising an electrically insulating layer formed on the first and second sides.

10. The circuit structure as in claim 8 further comprising an electrically insulting material formed between each of the first and second sides and an adjacent one of the electrical contacts.

Assignments (7)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040826/0821 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2009
From: MARINERO, ERNESTO E.
To: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
Reel/Frame 022157/0022 →