Method for forming strained channel PMOS devices and integrated circuits therefrom
View Patent ↗An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦10 10 dislocation lines/cm 2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×10 15 cm −2 , at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).
1. A method of forming an integrated circuit (IC) including a plurality of compressively strained PMOS devices, comprising:
providing a substrate wafer having a semiconductor surface including at least one PMOS region;
forming a patterned gate stack comprising a gate electrode on a gate dielectric on a surface of said PMOS region;
implanting said PMOS region on at least opposing sides of said gate stack using implant conditions comprising at least one compressive strain inducing specie selected from Ge, Sn and Pb, at a dose ≧1×10 15 cm −2 , and at an implantation temperature for said wafer during said implanting in a temperature range ≦273 K, wherein said implant conditions are sufficient to form an amorphous region;
annealing said wafer using annealing conditions comprising a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at said peak temperature of ≦10 seconds, wherein said amorphous region recrystallizes by solid phase epitaxy (SPE), and
completing fabrication of said PMOS device.
2. The method of claim 1 , wherein said implantation temperature is from 173K to 273K.
3. The method of claim 1 , wherein said annealing comprises a 1050° C. to 1150° C. spike anneal and a laser anneal at 1200 to 1300° C. for <10 msec.
4. The method of claim 3 , wherein said spike anneal precedes said laser anneal.
5. The method of claim 3 , wherein said laser anneal precedes said spike anneal.
6. The method of claim 1 , wherein said implanting occurs before said forming said patterned gate stack.
7. The method of claim 1 , wherein said implanting occurs after said forming said patterned gate stack.
8. The method of claim 1 , wherein said method further comprises forming spacers on sidewalls of said gate stack, wherein said implanting occurs after said forming said patterned gate stack and before said forming said spacers.
9. The method of claim 1 , further comprising co-implanting at least one dislocation pinning species selected from C, N and F with said implanting using a dose from 2×10 14 to 5×10 15 cm −2 in an energy range from 3 to 30 keV.
10. The method of claim 1 , wherein said at least one compressive strain inducing specie consists essentially of said Sn.
11. The method of claim 1 , wherein an energy for said implanting is from 20 keV to 300 keV.
12. A method of forming an integrated circuit (IC) including a plurality of compressively strained PMOS devices, comprising:
providing a substrate wafer having a semiconductor surface including at least one PMOS region;
forming a patterned gate stack comprising a gate electrode on a gate dielectric on a surface of said PMOS region;
implanting said PMOS region on opposing sides of said gate stack using implant conditions comprising Sn, at a dose between 5×10 15 cm −2 and 5×10 6 cm −2 , and an implantation temperature of said wafer during said implanting in a temperature range from 77 K to 273 K, wherein said implant conditions are sufficient to form an amorphous region;
annealing wafer using annealing conditions comprising a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at said peak temperature of ≦1 second, wherein said amorphous region recrystallizes by solid phase epitaxy (SPE), and
completing fabrication of said PMOS device.
13. The method of claim 12 , wherein said annealing comprises a 1050° C. to 1150° C. spike anneal and a laser anneal at 1200 to 1300° C. for <10 msec, further wherein said laser anneal precedes said spike anneal.