System and method for funds recovery from an integrated postal security device
View Patent ↗Systems and methods for providing funds recovery for mailing machines including integrated circuits such as those used in postal security devices are described, and in certain configurations, systems and methods for recovering data such as postal funds records from a partially disabled single integrated circuit in a postal security device are described.
1. A mailing machine for printing evidence of postage payment on mail pieces comprising:
a printer subsystem for printing indicia on a mail pieces;
a first processor operatively connected to the printer subsystem; and
a postal security device operatively connected to the first processor, the postal security device comprising a primary single integrated circuit including:
a postal security device processor used to process requests for the evidence of postage payment;
a plurality of non-volatile memory registers operatively connected to the postal security device processor for storing postal funds record data; and
a primary bus and control circuit operatively connecting the postal security device processor to the non-volatile memory registers for read and write access;
a secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers, wherein,
the secondary memory access device erases a secure memory location before providing read only access to the plurality of non-volatile memory registers.
2. The mailing machine according to claim 1 , wherein,
the secondary memory access device comprises a state machine and bus multiplexor and a write disable circuit.
3. The mailing machine according to claim 1 , wherein the postal security device further comprises:
a first power circuit for powering the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second power circuit for providing emergency power and powering the secondary memory access device and alternatively powering the plurality of non-volatile memory registers.
4. The mailing machine according to claim 2 , wherein the postal security device further comprises:
a first clock circuit for providing clock signals to the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers.
5. The mailing machine according to claim 3 , wherein:
the state machine erases includes a write disable circuit for disabling write access to the plurality of postal security data registers; and
the state machine erases includes a postal security device processor disable circuit for disabling the postal security device processor.
6. The mailing machine according to claim 5 , wherein, the write disable circuit is driven when the emergency power is present.
7. The mailing machine according to claim 3 , wherein:
the state machine serially outputs the data stored in the plurality of postal security data registers after the emergency power is detected.
8. The mailing machine according to claim 1 , wherein:
the a primary single integrated circuit includes a first JTAG subsystem; and
the secondary memory access device comprises a second JTAG subsystem.
9. A postal security device for processing requests for evidence of postage payment comprising a primary single integrated circuit including:
a postal security device processor used to process the requests for evidence of postage payment;
a plurality of non-volatile memory registers operatively connected to the postal security device processor for storing postal funds record data; and
a primary bus and control circuit operatively connecting the postal security device processor to the non-volatile memory registers for read and write access;
a secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers, wherein,
the secondary memory access device erases a secure memory location before providing read only access to the plurality of non-volatile memory registers.
10. The postal security device according to claim 9 , wherein,
the secondary memory access device comprises a state machine and bus multiplexor and a write disable circuit.
11. The postal security device according to claim 9 , further comprising:
a first power circuit for powering the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second power circuit for providing emergency power and powering the secondary memory access device and alternatively powering the plurality of non-volatile memory registers.
12. The postal security device according to claim 10 , further comprising:
a first clock circuit for providing clock signals to the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers.
13. The postal security device according to claim 11 , wherein:
the state machine erases includes a write disable circuit for disabling write access to the plurality of postal security data registers; and
the state machine erases includes a postal security device processor disable circuit for disabling the postal security device processor.
14. The postal security device according to claim 13 , wherein, the write disable circuit is driven when the emergency power is present.
15. The postal security device according to claim 11 , wherein:
the state machine serially outputs the data stored in the plurality of postal security data registers after the emergency power is detected.
16. The postal security device according to claim 9 , wherein:
the a primary single integrated circuit includes a first JTAG subsystem; and
the secondary memory access device comprises a second JTAG subsystem.