System and method for data recovery in a disabled integrated circuit
View Patent ↗Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.
1. An application specific integrated circuit comprising:
a core processor used to access a plurality of non-volatile memory registers during normal operation of the circuit;
a primary bus and control circuit operatively connecting the core processor to the non-volatile memory registers for read and write access;
a secondary memory access device operatively connected to the non-volatile memory registers, wherein the secondary memory access device erases data in a secure memory location before providing read only access to the plurality of non-volatile memory registers in a non-normal operation read mode.
2. The application specific integrated circuit according to claim 1 , wherein,
the secondary memory access device comprises a state machine, a bus multiplexor and a write disable circuit configured to control access to the plurality of non-volatile memory registers.
3. The application specific integrated circuit according to claim 1 , further comprising:
a first power circuit for powering the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second power circuit for providing power to the secondary memory access device and alternatively powering the plurality of non-volatile memory registers in the non-normal operation read mode.
4. The application specific integrated circuit according to claim 2 , further comprising:
a first clock circuit for providing clock signals to the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers in the non-normal operation read mode.
5. The application specific integrated circuit according to claim 3 , wherein:
the secondary memory access device comprises a state machine that includes a relatively small number of gates in the application specific integrated circuit and includes a write disable circuit for disabling write access to the plurality of non-volatile memory registers; and
the state machine includes a core processor disable circuit for disabling the core processor.
6. The application specific integrated circuit according to claim 5 , wherein:
the write disable circuit is driven when the second power signal is present.
7. An application specific integrated circuit comprising:
a core processor used to access a plurality of non-volatile memory registers during normal operation of the circuit;
a primary bus and control circuit operatively connecting the core processor to the non-volatile memory registers for read and write access;
a dual-port secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers in a non-normal operation read mode;
a first power circuit for powering the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit; and
a second power circuit for providing power to the secondary memory access device and alternatively powering the plurality of non-volatile memory registers in the non-normal operation read mode,
wherein:
the dual-port secondary memory access device erases a secure memory location before providing read only access to the plurality of non-volatile memory registers.
8. The application specific integrated circuit according to claim 3 , wherein:
the dual-port secondary memory access device serially outputs the data stored in the plurality of non-volatile memory registers after the second power signal is detected.
9. The application specific integrated circuit according to claim 1 , further comprising a first JTAG subsystem, wherein, the secondary memory access device comprises a second JTAG subsystem.
10. The application specific integrated circuit according to claim 3 , further comprising:
a fuse connected to the second power signal is configured to blow when the second power signal is applied.
11. The application specific integrated circuit according to claim 3 , wherein:
the dual-port secondary memory access device includes a charge pump clock disable circuit for disabling write access to the plurality of non-volatile memory registers.
12. An application specific integrated circuit comprising:
a core processor used to access a plurality of non-volatile memory registers during normal operation of the circuit;
a primary bus and control circuit operatively connecting the core processor to the non-volatile memory registers for read and write access;
a dual-port secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers in a non-normal operation read mode;
a first power circuit for powering the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit; and
a second power circuit for providing power to the secondary memory access device and alternatively powering the plurality of non-volatile memory registers in the non-normal operation read mode,
wherein:
the dual-port secondary memory access device reads a memory access address range register before providing read only access to the plurality of non-volatile memory registers indicated by the data read from the memory access address range register.
13. An application specific integrated circuit comprising:
a core processor used to access a plurality of non-volatile memory registers during normal operation of the circuit;
a primary bus and control circuit operatively connecting the core processor to the non-volatile memory registers for read and write access;
a dual-port secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers in a non-normal operation read mode and wherein the dual-port secondary memory access device reads a memory access address range register before providing read only access to the plurality of non-volatile memory registers indicated by the data read from the memory access address range register.
14. The application specific integrated circuit according to claim 13 , wherein,
the secondary memory access device comprises a state machine, a second bus and a write disable circuit configured to control access to the plurality of non-volatile memory registers.
15. The application specific integrated circuit according to claim 13 , further comprising:
a first power circuit for powering the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second power circuit for providing power to the secondary memory access device and alternatively powering the plurality of non-volatile memory registers in the non-normal operation read mode.
16. The application specific integrated circuit according to claim 14 , further comprising:
a first clock circuit for providing clock signals to the core processor, the plurality of non-volatile memory registers, and the primary bus and control circuit;
a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers in the non-normal operation read mode.
17. The application specific integrated circuit according to claim 15 , wherein:
the state machine includes a write disable circuit for disabling write access to the plurality of non-volatile memory registers; and
the dual-port secondary memory access device includes a core processor disable circuit for disabling the core processor.
18. The application specific integrated circuit according to claim 17 , wherein:
the write disable circuit is driven when the second power signal is present.
19. The application specific integrated circuit according to claim 13 , further comprising a first JTAG subsystem, wherein, the secondary memory access device comprises a second JTAG subsystem.
20. The application specific integrated circuit according to claim 15 , further comprising:
a fuse connected to the second power signal is detected configured to blow when the second power signal is applied.
21. The application specific integrated circuit according to claim 7 , wherein the dual-port secondary memory access device comprises a virtual dual-port secondary memory access device.
22. The application specific integrated circuit according to claim 12 , wherein the dual-port secondary memory access device comprises a virtual dual-port secondary memory access device.
23. The application specific integrated circuit according to claim 7 , wherein the dual-port secondary memory access device comprises a state machine that includes a relatively small number of gates in the application specific integrated circuit.
24. The application specific integrated circuit according to claim 12 , wherein the dual-port secondary memory access device comprises a state machine that includes a relatively small number of gates in the application specific integrated circuit.
25. The application specific integrated circuit according to claim 13 , wherein the dual-port secondary memory access device comprises a virtual dual-port secondary memory access device.
26. The application specific integrated circuit according to claim 13 , wherein the dual-port secondary memory access device comprises a physical dual-port secondary memory access device.
27. The application specific integrated circuit according to claim 13 , wherein the dual-port secondary memory access device comprises a state machine that includes a relatively small number of gates in the application specific integrated circuit.