Offline synchronous rectifier circuit with turned-on arbiter and phase-lock for switching power converters
View Patent ↗A synchronous rectifier circuit of a switching power converter is provided and includes first and second power transistors and first and second diodes connected to a transformer and an output of the power converter for rectifying. An arbiter circuit generates a lock signal to prevent the second power transistor from being turned on when the first power transistor is turned on. A controller generates a drive signal to control the first power transistor according to an on signal and an off signal. A phase-lock circuit generates the off signal according to the on signal. The on signal is enabled once the first diode is forward biased. The one signal enables the drive signal for turning on the first power transistor. The off signal disables the drive signal for turning off the first power transistor. The off signal is enabled before the disabling of the on signal.
1. A synchronous rectifier circuit of a switching power converter, comprising:
a power transistor and a diode coupled to a transformer and an output of the switching power converter for rectifying;
a controller generating a drive signal to control the power transistor in response to an on signal and an off signal; and
a phase-lock circuit generating the off signal in accordance with the on signal;
wherein the on signal is enabled once the diode is forward biased; and
wherein the on signal is coupled to enable the drive signal for turning on the power transistor, and the off signal is coupled to disable the drive signal for turning off the power transistor;
wherein the phase-lock circuit comprises:
a charging circuit generating a ramp signal when the on signal is enabled; and
a sampled circuit generating a hold signal in accordance with the level of the ramp signal;
a comparator generating the off signal in response to comparison of the ramp signal and the hold signal;
wherein the level of the hold signal is correlated to the period of the on signal.
2. The synchronous rectifier circuit as claimed in claim 1 further comprising:
a lock circuit generating a lock signal in response to the enabling of the drive signal;
wherein the lock signal is disabled in response to the disabling of the on signal, and the drive signal can only be enabled once the lock signal is disabled.
3. The synchronous rectifier as claimed in claim 1 , wherein the off signal is enabled before the disabling of the on signal.
4. The synchronous rectifier circuit as claimed in claim 1 , wherein the controller comprises:
a latch circuit generating the drive signal to control of the power transistor;
wherein the drive signal is enabled in response to the enabling of the on signal, and the drive signal is disabled in response to the enabling of the off signal.
5. The synchronous rectifier circuit as claimed in claim 1 further comprising:
a maximum-period circuit generating a maximum-period signal;
wherein the maximum-period signal is coupled to turn off the power transistor for limiting the maximum period of the power transistor.
6. The synchronous rectifier circuit as claimed in claim 1 further comprising:
an inhibit circuit generating an inhibit signal;
wherein the inhibit signal is a one-shot signal that coupled to inhibit the turning on of the power transistor after the power transistor is turned off.