Semiconductor memory device and driving method for the same

1. A semiconductor memory device comprising:

a first well of a first conductivity type, a second well of the first conductivity type and a third well of a second conductivity type formed in a substrate:

a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well;

a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line;

a first transistor formed in the first well for applying a voltage to the diffusion bit line; and

a diode formed in the third well, the diode being formed of the third well and a diffusion layer of the first conductivity type formed in an upper portion of the third well,

wherein the diffusion bit line, the diode and a source of the first transistor are electrically connected with one another.

2. The device of claim 1 , further comprising:

a fourth well of the first conductivity type formed in the substrate; and

a second transistor formed in the fourth well, the second transistor having a source connected with a ground potential and a drain electrically connected with the third well.

3. The device of claim 1 , further comprising:

a plurality of layers of metal interconnects formed above the substrate,

wherein the diffusion bit line and the diode are electrically connected with each other via a first-layer metal interconnect among the plurality of metal interconnects that is located closest to the substrate.

4. The device of claim 1 , wherein the third well is connected with a potential control circuit for controlling the potential of the third well.

5. The device of claim 1 , wherein each of the semiconductor memory elements has a gate insulating film including a charge trap film formed on the substrate and a gate electrode formed on the gate insulating film.

6. A semiconductor memory device comprising:

a first well of a first conductivity type, a second well of the first conductivity type and a third well of the first conductivity type formed in a substrate:

a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well;

a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line;

a first transistor formed in the first well for applying a voltage to the diffusion bit line; and

a second transistor formed in the third well,

wherein the diffusion bit line, a drain of the second transistor and a source of the first transistor are electrically connected with one another, and

a source of the second transistor is connected with a ground potential.

7. The device of claim 6 , further comprising:

a plurality of layers of metal interconnects formed above the substrate,

wherein the diffusion bit line and the drain of the second transistor are electrically connected with each other via a first-layer metal interconnect among the plurality of metal interconnects that is located closest to the substrate.

8. The device of claim 6 , wherein the diffusion bit line and the drain of the second transistor are in contact with each other.

9. The device of claim 6 , wherein a gate electrode of the second transistor is connected with a gate potential control circuit for controlling the gate potential of the second transistor.

10. The device of claim 6 , wherein each of the semiconductor memory elements has a gate insulating film including a charge trap film formed on the substrate and a gate electrode formed on the gate insulating film.

11. A driving method for a semiconductor memory device comprising: a first well of a first conductivity type, a second well of the first conductivity type, a third well of a second conductivity type and a fourth well of the first conductivity type formed in a substrate: a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well; a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line; a first transistor formed in the first well for applying a voltage to the diffusion bit line; a diode formed in the third well, the diode being formed of the third well and a diffusion layer of the first conductivity type formed in an upper portion of the third well; a second transistor formed in the fourth well with a source grounded; and a potential control circuit for controlling the potential of the third well, wherein the diffusion bit line, the diode and a source of the first transistor are electrically connected with one another, a drain of the second transistor is electrically connected with the third well, and the source of the second transistor is connected with a ground potential, the method comprising:

during actual operation of applying a bit line drive voltage to the diffusion bit line, applying a voltage equal to or higher than the bit line drive voltage to the third well with the potential control circuit while fixing a gate voltage of the second transistor to the ground potential to put the second transistor in an OFF state.

12. A driving method for a semiconductor memory device comprising: a first well of a first conductivity type, a second well of the first conductivity type and a third well of the first conductivity type formed in a substrate: a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well; a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line; a first transistor formed in the first well for applying a voltage to the diffusion bit line; and a second transistor formed in the third well, wherein the diffusion bit line, a drain of the second transistor and a source of the first transistor are electrically connected with one another, and a source of the second transistor is connected with a ground potential, the method comprising:

during actual operation of applying a bit line drive voltage to the diffusion bit line, fixing a gate voltage of the second transistor to the ground potential to put the second transistor in an OFF state.