FRAMEWORK FOR RESULTS INTERPRETATION AND GUIDED REFINEMENT OF SPECIFICATIONS FOR PLC LOGIC VERIFICATION
A system and method for interpreting formal verification results of PLC logic code used to control a manufacturing process, or other automated process, where the interpretation process does not require highly skilled technicians having significant experience in computer and mathematical algorithms. The verification process includes providing a verification results summary to check the compliance of the code with respect to the specifications. The verification results summary is analyzed and categorized to determine whether violations or errors are found in the results. The results can be depicted by assertion trees if a direct assertion between the PLC logic and the specifications can be provided. Alternatively, the results can be depicted by a reduced ladder logic if a direct assertion between the PLC logic and the specifications cannot be provided and a simulation is required. The specification refinement suggestions will be provided if the critical variable for violations is identified.
1 . A method for verifying a manufacturing process, said method comprising:
providing a verifier tool that represents the manufacturing process by mathematical models and algorithms;
inputting programmable logic controller (PLC) logic code and specifications to the verifier tool;
providing a results summary of the simulated manufacturing process from the verifier tool;
analyzing the results summary to determine whether violations are found in the simulated manufacturing process;
displaying the results using an assertion tree if a direct assertion is possible between the PLC logic and the specifications; and
displaying the results using a reduced ladder logic if a direct assertion between the PLC logic and the specifications is not possible, where a simulation is required.
2 . The method according to claim 1 further comprising viewing the assertion tree or the reduced ladder logic to determine if there are errors in the process, and documenting the errors if they are identifiable.
3 . The method according to claim 1 further comprising viewing the reduced ladder logic or the assertion tree, determining that the process includes errors, determining that the specifications seems to be invalid or incomplete, and refining the specifications in the verifier tool.
4 . The method according to claim 1 further comprising viewing the assertion tree or the reduced ladder logic, determining that the process seems to have errors, determining whether refinement of the specification is possible, and refining the specifications in the verifier tool.
5 . The method according to claim 1 further comprising displaying critical variables and values in response to analyzing the results summary.
6 . The method according to claim 1 wherein the results summary is provided as a direct assertion.
7 . The method according to claim 6 wherein the results summary can show no violations if direct assertion between the PLC logic and the specifications is possible.
8 . The method according to claim 6 wherein the results summary can show violations at all scenarios if direct assertion between the PLC logic and the specifications is possible.
9 . The method according to claim 6 wherein the results summary can show no violations if direct assertion between the PLC logic and the specifications is not possible.
10 . The method according to claim 6 wherein the results summary can show violations at all scenarios if direct assertion between the PLC logic and the specifications is not possible.
11 . The method according to claim 6 wherein the results summary can show violations at some scenarios if direct assertion between the PLC logic and the specifications is not possible.
12 . A method for verifying an automated process, said method comprising:
representing the automated process by mathematical models and algorithm;
operating the automated process using the mathematical models and algorithms in combination with programmable logic controller (PLC) logic code and specifications;
providing a results summary of the automated process;
analyzing the results summary to determine whether violations are found in the automated process; and
displaying the results using an assertion tree or reduced ladder logic.
13 . The method according to claim 12 further comprising viewing the assertion tree or the reduced ladder logic to determine if there are errors in the process, and documenting the errors if they are identifiable.
14 . The method according to claim 12 further comprising viewing the reduced ladder logic or the assertion tree, determining that the process includes errors, determining that the specifications seems to be invalid or incomplete, and refining the specifications in the verifier tool.
15 . The method according to claim 12 further comprising viewing the assertion tree or the reduced ladder logic, determining that the process seems to have errors, determining whether refinement of the specification is possible, and refining the specifications in the verifier tool.
16 . The method according to claim 12 wherein the results summary can show no violations if direct assertion between the PLC logic and the specifications is possible.
17 . The method according to claim 12 wherein the results summary can show violations at all scenarios if direct assertion between the PLC logic and the specifications is possible.
18 . The method according to claim 12 wherein the results summary can show no violations if direct assertion between the PLC logic and the specifications is not possible.
19 . The method according to claim 12 wherein the results summary can show violations at all scenarios if direct assertion between the PLC logic and the specifications is not possible.
20 . The method according to claim 12 wherein the results summary can show violations at some scenarios if direct assertion between the PLC logic and the specifications is not possible.