Display substrate having quantum well for improved electron mobility and display device including the same
View Patent ↗Provided are a display substrate and a display device including the same. The display substrate includes: gate wiring; a first semiconductor pattern formed on the gate wiring and having a first energy bandgap; a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap; data wiring formed on the first semiconductor pattern; and a pixel electrode electrically connected to the data wiring. Because the second energy bandgap is larger than the first energy bandgap, a quantum well is formed in the first semiconductor pattern, enhancing electron mobility therein.
1. A display substrate comprising:
gate wiring;
a first semiconductor pattern formed on the gate wiring and having a first energy bandgap;
a second semiconductor pattern formed on the first semiconductor pattern, wherein the second semiconductor pattern comprises an oxide and has a second energy bandgap which is greater than the first energy bandgap;
data wiring formed on the first semiconductor pattern; and
a pixel electrode electrically connected to the data wiring.
2. The display substrate of claim 1 , wherein the second semiconductor pattern is disposed under the data wiring and forms an ohmic contact with the data wiring.
3. The display substrate of claim 1 , wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.
4. The display substrate of claim 1 , wherein the first semiconductor pattern comprises amorphous silicon.
5. The display substrate of claim 1 , further comprising a third semiconductor pattern formed between the gate wiring and the first semiconductor pattern and having a third energy bandgap which is greater than the first energy bandgap, wherein the display device is configured to form a quantum well in the first semiconductor pattern.
6. The display substrate of claim 1 , further comprising a gate insulating film formed between the gate wiring and the first semiconductor pattern, wherein a quantum well is formed in the first semiconductor pattern.
7. The display substrate of claim 1 , further comprising an ohmic contact layer disposed on the first semiconductor pattern and forming an ohmic contact with the data wiring.
8. The display substrate of claim 1 , wherein a thickness of the first semiconductor pattern is approximately 200 Å or less.
9. A display substrate including a thin film transistor comprising:
a gate electrode;
a first semiconductor pattern formed on the gate electrode and comprising amorphous silicon;
a second semiconductor pattern formed on the first semiconductor pattern and comprising an oxide;
a source electrode formed on the second semiconductor pattern; and
a drain electrode formed on the second semiconductor pattern and separated from the source electrode.
10. The display substrate of claim 9 , wherein the second semiconductor pattern forms an ohmic contact with each of the source electrode and the drain electrode.
11. The display substrate of claim 9 , wherein the first semiconductor pattern has a first energy bandgap, and the second semiconductor pattern has a second energy bandgap which is greater than the first energy bandgap.
12. The display substrate of claim 9 , further comprising a gate insulating film formed between the gate wiring and the first semiconductor pattern, wherein a quantum well is formed in the first semiconductor pattern.
13. The display substrate of claim 9 , wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.
14. The display substrate of claim 9 , wherein a thickness of the first semiconductor pattern is approximately 200 Å or less.
15. A display device comprising:
a first display substrate;
a second display substrate facing the first display substrate; and
a liquid crystal layer interposed between the first display substrate and the second display substrate,
wherein the first display substrate comprises:
gate wiring;
a first semiconductor pattern formed on the gate wiring and having a first energy bandgap;
a second semiconductor pattern formed on the first semiconductor pattern,
wherein the second semiconductor pattern comprises an oxide and has a second energy bandgap which is greater than the first energy bandgap;
data wiring formed on the first semiconductor pattern; and
a pixel electrode electrically connected to the data wiring.
16. The display device of claim 15 , wherein the second semiconductor pattern is disposed under the data wiring and forms an ohmic contact with the data wiring.
17. The display device of claim 15 , wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.
18. The display device of claim 15 , wherein the first semiconductor pattern comprises amorphous silicon.
19. The display device of claim 15 , further comprising a third semiconductor pattern formed between the gate wiring and the first semiconductor pattern and having a third energy bandgap which is greater than the first energy bandgap, wherein the display device is configured to form a quantum well in the first semiconductor pattern.
20. The display device of claim 15 , wherein a thickness of the first semiconductor pattern is approximately 200 Å or less.