Charge pump circuit
View Patent ↗There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.
1. A charge pump circuit comprising:
a charge pump circuit body, including a plurality of charge transfer elements coupled in series and a plurality of capacitive elements each coupled to a coupling path between adjacent charge transfer elements, which boosts an external power supply voltage supplied from an external power supply to the charge transfer elements by charging and discharging adjacent capacitive elements alternately and outputs a boosted voltage higher than the external power supply voltage;
a level detection circuit which compares the boosted voltage outputted from the charge pump circuit body with a predetermined reference voltage and outputs a level detection signal according to a comparison result;
an oscillator circuit which outputs a clock signal in response to the level detection signal outputted from the level detection circuit; and
a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing the level detection signal outputted from the level detection circuit to the clock signal outputted from the oscillator circuit,
wherein the capacitive elements in the charge pump circuit body are charged and discharged in response to the clock signal outputted from the oscillator circuit and the synchronization detection signal outputted from the detection signal synchronization circuit,
wherein the detection signal synchronization circuit includes an RS flip-flop, and
wherein in the RS flip-flop, the level detection signal outputted from the level detection circuit is supplied to a reset terminal, the clock signal outputted from the oscillator circuit is supplied to a set terminal, and the synchronization detection signal is outputted from an inverting output terminal.