Intelligent cache injection
View Patent ↗A first cache simultaneously broadcasts, in a single message, a request for a cache line and a request to accept a future related evicted cache line to multiple other caches. Each of the multiple other caches evaluate their occupancy to derive an occupancy value that reflects their ability to accept the future related evicted cache line. In response to receiving a requested cache line, the first cache evicts the related evicted cache line to the cache with the highest occupancy value.
1. A method of intelligently injecting a cache line, the method comprising:
simultaneously broadcasting, from a first cache to multiple other caches, a single message that includes a request for a cache line and a request for another cache to accept a future evicted cache line;
deriving an occupancy value for each of the multiple other caches, wherein the occupancy value reflects an ability to accept the future evicted cache line, wherein the occupancy value is computed by an algorithm having operands that are based on how many second class lines are in a same cache associative set compared to first class lines, wherein second class lines contain cache entries have been previously injected from another cache, wherein first class lines have been stored directly from a coupled processor that utilizes a directly coupled cache, and wherein first class lines lower the occupancy value and second class lines raise the occupancy value; and
evicting and transmitting an evicted cache line to a receiver cache from the multiple other caches, wherein the receiver cache has a highest occupancy value compared to other caches from the multiple other caches.
2. The method of claim 1 , wherein the evicting and transmitting of the evicted cache line is performed in response to the first cache receiving a requested cache line from a provider cache from the multiple other caches.
3. A system comprising:
a plurality of processors;
a first cache directly coupled to and dedicated to use by a first processor from the plurality of processors; and
multiple other caches, wherein a different cache from the multiple other caches is coupled to and dedicated to each of other processors from the plurality of processors, wherein the first processor:
simultaneously broadcasts, to multiple other caches that are coupled to and dedicated to the other processors, a request for a cache line and a request for one of the multiple other caches to accept a future evicted cache line;
derives an occupancy value for each of the multiple other caches, wherein the occupancy value reflects an ability to accept the future evicted cache line, wherein the occupancy value is computed by an algorithm having operands that are based on how many second class lines are in a same cache associative set compared to first class lines, wherein second class lines contain cache entries have been previously injected from another cache, wherein first class lines have been stored directly from a coupled processor that utilizes a directly coupled cache, and wherein first class lines lower the occupancy value and second class lines raise the occupancy value; and
in response to the first cache receiving a requested cache line from a provider cache from the multiple other caches, evicts and transmits an evicted cache line to a receiver cache from the multiple other caches, wherein the receiver cache has a highest occupancy value compared to other caches from the multiple other caches.
4. The system of claim 3 , wherein the first cache and each of the multiple other caches are each associated with different dedicated processors that each respectively utilize only one of the first cache and the other multiple other caches.
5. The system of claim 4 , wherein the provider cache and the receiver cache are a same cache.
6. A computer-readable storage medium on which is encoded a computer program, the computer program comprising computer executable instructions configured for:
simultaneously broadcasting, from a first cache to multiple other caches, a request for a cache line and a request for another cache to accept a future evicted cache line;
deriving an occupancy value for each of the multiple other caches, wherein the occupancy value reflects an ability to accept the future evicted cache line, wherein the occupancy value is computed by an algorithm having operands that are based on how many second class lines are in a same cache associative set compared to first class lines, wherein second class lines contain cache entries have been previously injected from another cache, wherein first class lines have been stored from a coupled processor that directly utilizes a directly coupled cache, and wherein first class lines lower the occupancy value and second class lines raise the occupancy value; and
in response to the first cache receiving a requested cache line from a provider cache from the multiple other caches, evicting and transmitting an evicted cache line to a receiver cache from the multiple other caches, wherein the receiver cache has a highest occupancy value compared to other caches from the multiple other caches.
7. The computer-readable storage medium of claim 6 , wherein the first cache and each of the multiple other caches are each associated with different dedicated processors that each respectively utilize only one of the first cache and the other multiple other caches.
8. The computer-readable storage medium of claim 6 , wherein the provider cache and the receiver cache are a same cache.