Method for the data transfer between at least two clock domains
View Patent ↗The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK 1 ) and at least one additional clock domain having a second clock rate (CLK 2 ), comprising the following for the transfer of data from the first to the second clock domain (CLK 1 , CLK 2 ): reading in of a data item in accordance with the first clock rate (CLK 1 ) into a first memory ( 11 ), and locking of the first memory after saving the data item, signalizing a transfer start after saving the data item in the first memory ( 11 ) by means of a transfer start signal (TS), reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock signal (CLK 2 ), processing the transfer start signal (TS) according to the second clock signal (CLK 2 ) for generating a transfer end signal (TD), processing the transfer end signal (TD) according to the first clock signal (CLK 1 ) for generating a release signal (TD′) and releasing the first memory as a function of the release signal (TD′).
1. A method for transferring data between a first clock domain having a first clock rate and at least one additional clock domain having a second clock rate, wherein the data is transferred from the first clock domain to the at least one additional clock domain, the method comprising:
reading in of a data item in accordance with the first clock rate into a first memory, and locking of the first memory after saving the data item,
signalizing a transfer start after saving the data item in the first memory by means of a transfer start signal,
reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock rate,
processing the transfer start signal according to the second clock rate for generating a transfer end signal,
processing the transfer end signal according to the first clock rate for generating a release signal and releasing the first memory as a function of the release signal,
wherein a level change of the transfer end signal is generated according to a default number of clock period of the second clock rate after a level change of the transfer start signal, and
wherein the generating of a level change of the transfer end signal occurs utilizing a first subsidiary signal, which is generated according to a default number of clock periods of the second clock rate after a level change of the transfer start signal.
2. The method according to claim 1 , wherein a transfer start is signalized via a level change of the transfer start signal.
3. The method according to claim 2 , wherein a level change of the transfer end signal is generated according to a default number of clock period of the second clock rate after a level change of the transfer start signal.
4. The method according to claim 3 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
5. The method according to claim 2 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
6. The method according to claim 1 , wherein the first subsidiary signal is a signal impulse, the duration of which corresponds to that of a clock period of the second clock rate.
7. The method according to claim 6 , wherein the transfer end signal is delayed as opposed to the beginning of a signal impulse of the subsidiary signal such that a level change of the transfer end signal is present after the beginning of default number of clock periods of the second clock rate after the beginning of the signal impulse of the subsidiary signal.
8. The method according to claim 6 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
9. The method according to claim 7 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
10. The method according to claim 1 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
11. The method according to claim 1 , wherein the transfer end signal is delayed as opposed to the beginning of a signal impulse of the subsidiary signal such that a level change of the transfer end signal is present after the beginning of default number of clock periods of the clock signal after the beginning of the signal impulse of the subsidiary signal.
12. The method according to claim 11 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
13. The method according to claim 1 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
14. The method according to claim 1 , wherein a level change of the release signal is generated according to a default number of clock periods of the first clock rate after a level change of the transfer end signal.
15. A method for transferring data between a first clock domain having a first clock rate and at least one additional clock domain having a second clock rate, wherein the data is transferred from the at least one additional clock domain to the first clock domain, the method comprising:
reading in of a data item in accordance with the first clock rate into a first memory, and locking of the first memory after saving the data item,
signalizing a transfer start after saving the data item in the first memory by means of a transfer start signal,
reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock rate,
processing the transfer start signal according to the second clock signal for generating a transfer end signal,
processing the transfer end signal according to the first clock rate for generating a release signal and releasing the first memory as a function of the release signal,
wherein a level change of the transfer end signal is generated according to a default number of clock period of the second clock rate after a level change of the transfer start signal, and
wherein the generating of a level change of the transfer end signal occurs utilizing a first subsidiary signal, which is generated according to a default number of clock periods of the second clock after a level change of the transfer start signal.