IP Library Granted Patent US 7,902,532
Granted Patent B2
US 7,902,532 · App. 12/355,251 · Granted Mar 8, 2011

Systems and methods involving transducer signals

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Quick Facts
Patent No.
US 7,902,532
App. No.
12/355,251
Granted
Mar 8, 2011
Kind
B2
Abstract

A system for operating a transducer comprising, a first node connected to a first transducer, a first photo-activated switching device having a first source, a first drain connected to the first node, and a first gate operative to receive a first logic signal, a first terminal connected to the first source; a second photo-activated switching device having a second source connected to the first node, a second drain, and a second gate operative to receive a second logic signal, and a second terminal connected to the second drain.

Claims (38)

1. A system for operating a transducer comprising:

a first node connected to a first transducer;

a first photo-activated switching device having a first source, a first drain connected to the first node, and a first gate operative to receive a first logic signal;

a first terminal connected to the first source;

a second photo-activated switching device having a second source connected to the first node, a second drain, and a second gate operative to receive a second logic signal; and

a second terminal connected to the second drain.

2. The system of claim 1 , wherein the system further comprises:

a third photo-activated switching device having a third source connected to the first node, a third drain, and a third gate operative to receive a third logic signal; and

an output node connected to the third drain.

3. The system of claim 1 , wherein the first terminal is operative to drive the first transducer.

4. The system of claim 1 , wherein the second terminal is operative to drive the first transducer.

5. The system of claim 1 , wherein the first gate is connected to an output terminal of a processor.

6. The system of claim 1 , wherein the second gate is connected to an output terminal of a processor.

7. The system of claim 2 , wherein the third gate is connected to an output terminal of a processor.

8. The system of claim 2 , wherein the output node is connected to an input of a signal conditioning circuit.

9. The system of claim 8 , wherein the signal conditioning circuit is connected to a processor.

10. The system of claim 2 , wherein the output node is connected to an input of a processor.

11. The system of claim 1 , wherein the second terminal is a ground terminal.

12. A transducer signal control circuit comprising:

a first node connected to a first transducer;

a first photo-activated switching device having a first source, a first drain connected to the first node, and a first gate operative to receive a first logic signal;

a first terminal connected to the first source;

a second photo-activated switching device having a second source connected to the first node, a second drain, and a second gate operative to receive a second logic signal; and

a second terminal connected to the second drain.

13. The circuit of claim 12 , wherein the circuit further comprises:

a second node connected to a second transducer;

a third photo-activated switching device having a third source, a third drain connected to the second node, and a third gate operative to receive a third logic signal;

a third terminal connected to the third source;

a fourth photo-activated switching device having a fourth source connected to the second node, a fourth drain, and a fourth gate operative to receive a fourth logic signal; and

a fourth terminal connected to the fourth drain.

14. The circuit of claim 12 , wherein the circuit further comprises:

an output node; and

a fifth photo-activated switching device having a fifth source connected to the first node, a fifth drain connected to the output node, and a fifth gate operative to receive a fifth logic signal.

15. The circuit of claim 13 , wherein the circuit further comprises a sixth photo-activated switching device having a sixth source connected to the second node, a sixth drain connected to the output node, and a sixth gate operative to receive a sixth logic signal.

16. The circuit of claim 12 , wherein the first terminal is operative to drive the first transducer.

17. The circuit of claim 12 , wherein the second terminal is operative to drive the first transducer.

18. The circuit of claim 12 , wherein the first gate is connected to an output terminal of a processor.

19. The circuit of claim 12 , wherein the second gate is connected to an output terminal of a processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2020
From: GENERAL ELECTRIC COMPANY
To: BAKER HUGHES, A GE COMPANY, LLC
Reel/Frame 051624/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2009
From: WELLER, NATHAN ANDREW
To: GENERAL ELECTRIC COMPANY
Reel/Frame 022121/0384 →