Integrated clock and power distribution
An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure.
1. A semiconductor device comprising:
a semiconductor layer; and
a plurality of metal layers;
wherein a top metal layer and a top-1 metal layer are arranged as a full-dense-mesh distribution network,
the top metal layer comprises an integrated clock and power distribution network,
the top-1 metal layer comprises a low impedance underpass corresponding to the integrated clock and power distribution network,
the integrated clock and power distribution network includes a clock distribution network routed in a cut-out of a power distribution network on the top metal layer, and
the low impedance underpass on the top-1 metal layer is arranged such that the clock distribution network is coupled approximately 50% to the power distribution network on the top metal layer and is coupled approximately 50% to a ground potential on the top-1 metal layer.
2. The semiconductor device of claim 1 , wherein the integrated clock and power distribution network comprises a plurality of bow tie elements.
3. The semiconductor device of claim 1 , wherein the integrated clock and power distribution network comprises at least one of a portion of a bow tie element, a bow tie element, a plurality of bow tie elements, a half-bow tie element, an extended half-bow tie element, a three-half-bow tie element, a hyper-fine bow tie element, an X-tree element, an H-tree element, or additional wire.
4. The semiconductor device of claim 1 , wherein the clock distribution network provides for different x-axis and y-axis pitches.
5. The semiconductor device of claim 1 , wherein the clock distribution network provides fine pitch in a y-axis direction and coarse pitch in an x-axis direction.
6. A system comprising:
a semiconductor device;
a storage device;
a network device; and
an input device;
wherein the semiconductor device comprises:
a semiconductor layer, and
a plurality of metal layers,
wherein a top metal layer and a top-1 metal layer are arranged as a full-dense-mesh distribution network,
the top metal layer comprises an integrated clock and power distribution network,
the top-1 metal layer comprises a low impedance underpass corresponding to the integrated clock and power distribution network,
the integrated clock and power distribution network includes a clock distribution network routed in a cut-out of a power distribution network on the top metal layer, and
the low impedance underpass on the top-1 metal layer is arranged such that the clock distribution network is coupled approximately 50% to the power distribution network on the top metal layer and is coupled approximately 50% to a ground potential on the top-1 metal layer.
7. The system of claim 6 , wherein the integrated clock and power distribution network comprises at least one of a portion of a bow tile element, a bow tie element, a plurality of bow tie elements, a half-bow tie element, an extended half-bow tie element, a three-half-bow tie element, a hyper-fine bow tie element, an X-tree element, an H-tree element, or additional wire.
8. The system of claim 6 , wherein the clock distribution network provides for different x-axis and y-axis pitches.
9. The system of claim 6 , wherein the clock distribution network provides fine pitch in a y-axis direction and coarse pitch in an x-axis direction.