IP Library Granted Patent US 8,049,210
Granted Patent B2
US 8,049,210 · App. 12/356,390 · Granted Nov 1, 2011

Thin film transistor, matrix substrate, electrophoresis display device, and electronic apparatus

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Quick Facts
Patent No.
US 8,049,210
App. No.
12/356,390
Granted
Nov 1, 2011
Kind
B2
Abstract

Provided is a thin film transistor including a substrate, a source electrode and a drain electrode disposed above the substrate so as to oppose each other, an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region, and a gate electrode disposed opposite the organic semiconductor film via a gate insulating film. The gate electrode includes an aperture in the channel region.

Claims (42)

1. A thin film transistor comprising:

a substrate;

a source electrode and a drain electrode disposed above the substrate so as to oppose each other;

an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region; and

a gate electrode disposed opposite the organic semiconductor film via a gate insulating film,

wherein

the gate electrode includes an aperture at an area overlapping the channel region; and

the gate insulating film is disposed between the aperture of the gate electrode and the organic semiconductor film in plan view.

2. The thin film transistor according to claim 1 , wherein the gate electrode includes a path, in the channel region, connecting a region where the gate electrode overlaps the source electrode to a region where the gate electrode overlaps the drain electrode.

3. The thin film transistor according to claim 1 , wherein a projection region projected on the organic semiconductor film covers the aperture when the projection region is projected from an end of the aperture toward the interior side of the aperture at an angle of 45° from the direction perpendicular to the gate insulating film direction.

4. The thin film transistor according to claim 3 , wherein the aperture lies above the source electrode or the drain electrode.

5. The thin film transistor according to claim 1 , wherein the gate electrode includes a plurality of first wiring lines, in the channel region, extending in a first direction from the source electrode to the drain electrode and disposed with a certain distance therebetween.

6. The thin film transistor according to claim 1 , wherein the gate electrode includes a plurality of second wiring lines, in the channel region, extending in a second direction that intersects a first direction from the source electrode to the drain electrode and disposed with a certain distance therebetween.

7. The thin film transistor according to claim 6 , wherein the second wiring lines are connected to one another with a third wiring line extending in the first direction in a region outside the channel region.

8. The thin film transistor according to claim 1 , wherein the gate electrode includes, in the channel region, a plurality of first wiring lines extending in a first direction from the source electrode to the drain electrode and disposed with a certain distance therebetween and a plurality of second wiring lines extending in a second direction that intersects the first direction and disposed with a certain distance therebetween.

9. The thin film transistor according to claim 1 , wherein

the gate electrode includes a plurality of apertures in the channel region, and

the plurality of apertures are arranged in an array form.

10. A thin film transistor comprising:

a substrate;

a source electrode and a drain electrode disposed above the substrate so as to oppose each other;

an organic semiconductor film disposed between the source electrode and the drain electrode; and

a gate electrode disposed opposite a first face or a second face of the organic semiconductor film via a gate insulating film,

wherein

the gate electrode is an electroconductive film formed by solidifying a dispersion liquid containing electroconductive particles and having pores therein; and

the gate insulating film is disposed between the pores of the gate electrode and the organic semiconductor film in plan view.

11. A thin film transistor comprising:

a substrate;

a source electrode and a drain electrode disposed above the substrate so as to oppose each other;

an organic semiconductor film disposed between the source electrode and the drain electrode;

a gate electrode disposed opposite a first face or a second face of the organic semiconductor film via a gate insulating film,

wherein

the gate electrode includes a recess in the channel region that is a region lying between the source electrode and the drain electrode and overlapping the organic semiconductor film;

the gate insulating film is disposed between the recess of the gate electrode and the organic semiconductor film in plan view.

12. The thin film transistor according to claim 11 , wherein the thickness of the gate electrode at an area serving as the bottom of recess is 100 nm or less.

13. The thin film transistor according to claim 11 , wherein the thickness of the gate electrode at an area serving as the bottom of recess is 50 nm or less.

14. The thin film transistor according to claim 11 , wherein the gate electrode includes a laminated film of a first electroconductive film and a second electroconductive film, and the first electroconductive film is exposed to serve as the bottom of the recess.

15. The thin film transistor according to claim 14 , wherein the thickness of the first electroconductive film is 100 nm or less.

16. The thin film transistor according to claim 14 , wherein the thickness of the first electroconductive film is 50 nm or less.

17. A matrix substrate comprising a plurality of thin film transistors according to claim 1 .

18. An electrophoresis display device comprising the matrix substrate according to claim 17 .

19. An electronic apparatus comprising the electrophoresis display device according to claim 18 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SEIKO EPSON CORPORATION
To: E INK CORPORATION
Reel/Frame 047072/0325 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2009
From: AOKI, TAKASHI; MORIYA, SOICHI
To: SEIKO EPSON CORPORATION
Reel/Frame 022129/0645 →