Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
View Patent ↗Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.
1. A non-transitory machine readable medium containing executable computer program instructions which when executed by a data processing system cause the data processing system to perform a method of designing an integrated circuit (IC), the method comprising:
creating a representation of a shielding mesh in a representation of a design of the IC, the shielding mesh comprising a first single layer shielding mesh and a first double layer shielding mesh which is coupled to the first single layer shielding mesh;
creating a representation of a second shielding mesh having at least a first layer and having a first set of lines which are diagonally oriented relative to a second set of lines in the first single layer shielding mesh and are diagonally oriented relative to a third set of lines in the first double layer shielding mesh, wherein the second shielding mesh is inserted into an unshielded region of the first shielding mesh.
2. The non-transitory machine readable medium as in claim 1 wherein the first single layer shielding mesh is disposed in an nth layer of the representation of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth+1 layer of the representation of the IC, and the second shielding mesh is disposed in at least one of the nth layer and the nth+1 layer.
3. The non-transitory machine readable as in claim 2 wherein the first set of lines are oriented non-orthogonally relative to the second set of lines and to the third set of lines.
4. The non-transitory machine readable medium of claim 1 , wherein the first set of lines includes a first reference voltage line, and a second reference voltage line.
5. The non-transitory machine readable medium of claim 1 , further comprising
routing a signal line through the second shielding mesh.
6. A machine-implemented method to design an integrated circuit (IC), the method comprising:
creating a representation of a first shielding mesh in a representation of a design of the IC, the first shielding mesh comprising a first single layer shielding mesh and a first double layer shielding mesh which is coupled to the first single layer shielding mesh;
creating a representation of a second shielding mesh coupled to the first shielding mesh, the second shielding mesh having at least a first layer and having a first set of lines which are diagonally oriented relative to a second set of lines in the first single layer shielding mesh and are diagonally oriented relative to a third set of lines in the first double layer shielding mesh, wherein at least one of the creating the representation of the first shielding mesh and creating the representation of the second shielding mesh is performed by a processor, wherein the second shielding mesh is inserted into an unshielded region of the first shielding mesh.
7. The method of claim 6 wherein the first single layer shielding mesh is disposed in an nth layer of the representation of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth+1 layer of the representation of the IC, and the second shielding mesh is disposed in at least one of the nth layer and the nth+1 layer.
8. The method of claim 7 wherein the first set of lines are oriented non-orthogonally relative to the second set of lines and to the third set of lines.
9. The method of claim 6 , wherein the first set of lines includes a first reference voltage line, and a second reference voltage line.
10. The method of claim 6 , further comprising
routing a signal line through the second shielding mesh.
11. A system to design an integrated circuit (IC), comprising:
means for creating a representation of a first shielding mesh in a representation of a design of the IC, the first shielding mesh comprising a first single layer shielding mesh and a first double layer shielding mesh which is coupled to the first single layer shielding mesh;
means for creating a representation of a second shielding mesh coupled to the first shielding mesh, the second shielding mesh having at least a first layer and having a first set of lines which are diagonally oriented relative to a second set of lines in the first single layer shielding mesh and are diagonally oriented relative to a third set of lines in the first double layer shielding mesh, wherein the second shielding mesh is inserted into an unshielded region of the first shielding mesh.
12. The system of claim 11 wherein the first single layer shielding mesh is disposed in an nth layer of the representation of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth+1 layer of the representation of the IC, and the second shielding mesh is disposed in at least one of the nth layer and the nth+1 layer.
13. The system of claim 12 wherein the first set of lines are oriented non-orthogonally relative to the second set of lines and to the third set of lines.
14. The system of claim 11 , wherein the first set of lines includes a first reference voltage line, and a second reference voltage line.
15. The system of claim 11 , further comprising
means for routing a signal line through the second shielding mesh.