Method and apparatus to design an interconnection device in a multi-layer shielding mesh

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Quick Facts

Patent No.: US 8,386,979
App. No.: 12/358,208
Granted: Feb 26, 2013
Kind: B2

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Abstract

Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Claims (26)

1. A non-transitory machine readable medium containing executable computer program instructions which when executed by a data processing system cause the data processing system to perform a method of designing an integrated circuit (IC), the method comprising:

creating a representation of a shielding mesh in a representation of a design of the IC, the shielding mesh comprising a first single layer shielding mesh and a first double layer shielding mesh which is coupled to the first single layer shielding mesh, the first double layer shielding mesh comprising a first line and a second line in a first layer;

2. The non-transitory machine readable medium as in claim 1 wherein the interconnection device is one of (a) a transistor or (b) a fuse or (c) an anti-fuse.

3. The non-transitory machine readable medium as in claim 1 wherein the first single layer shielding mesh is disposed in an nth layer of the representation of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth +1 layer of the representation of the IC.

4. The non-transitory machine readable medium of claim 1 , wherein the first single layer shielding mesh comprises a first plurality of conductive lines in a first layer of the representation of the design of the IC, and the first double layer shielding mesh comprises a second plurality of conductive lines in the first layer and a third plurality of conductive lines in a second layer of the representation of the design of the IC.

5. The non-transitory machine readable medium of claim 1 , wherein the interconnection device is programmable.

6. The non-transitory machine readable medium of claim 1 , wherein the signal line is adjacent to the first line.

7. The non-transitory machine readable medium of claim 1 , wherein the representation of the design of the IC comprises an unshielded region.

8. An integrated circuit (IC) comprising:

a shielding mesh comprising a first single layer shielding mesh and a first double layer shielding mesh which is coupled to the first single layer shielding mesh, wherein the first double layer shielding mesh comprises a first line and a second line in a first layer;

an interconnection device connected to the first line in the first layer of the first double layer shielding mesh and connected to a signal line which is routed between the first line and the second line in the first layer of the first double layer shielding mesh.

9. The IC of claim 8 , wherein the interconnection device is one of (a) a transistor or (b) a fuse or (c) an anti-fuse.

10. The IC of claim 8 wherein the first single layer shielding mesh is disposed in an nth layer of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth +1 layer of the IC.

11. The IC of claim 8 , wherein the interconnection device is programmable.

12. The IC of claim 8 , wherein the signal line is adjacent to the first line.

13. The IC of claim 8 , wherein the IC comprises an unshielded region.

14. The IC of claim 8 , wherein the first single layer shielding mesh comprises a first plurality of conductive lines in a first layer of the IC, and the first double layer shielding mesh comprises a second plurality of conductive lines in the first layer and a third plurality of conductive lines in a second layer of the IC.

15. A method to design an integrated circuit, comprising:

creating a representation of an interconnection device connected to the first line which forms a portion of the first double layer shielding mesh in the first layer and connected to a signal line which is routed between the first line and the second line in the first layer of the first double layer shielding mesh, wherein at least one of the creating the representation of the shielding mesh and the creating the representation of the interconnection device is performed by a processor.

16. The method as in claim 15 wherein the interconnection device is one of (a) a transistor or (b) a fuse or (c) an anti-fuse.

17. The method as in claim 15 wherein the first single layer shielding mesh is disposed in an nth layer of the representation of the IC, and the first double layer shielding mesh is disposed in the nth layer and in an nth +1 layer of the representation of the IC.

18. The method as in claim 15 , wherein the first single layer shielding mesh comprises a first plurality of conductive lines in a first layer of the representation of the design of the IC, and the first double layer shielding mesh comprises a second plurality of conductive lines in the first layer and a third plurality of conductive lines in a second layer of the representation of the design of the IC.

19. The method as in claim 15 , wherein the interconnection device is programmable.

20. The method as in claim 15 , wherein the representation of the design of the IC comprises an unshielded region.