IP Library Granted Patent US 7,636,798
Granted Patent B2
US 7,636,798 · App. 12/359,446 · Granted Dec 22, 2009

Methods and systems for integrating unique information in SAS interface components

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,636,798
App. No.
12/359,446
Granted
Dec 22, 2009
Kind
B2
Abstract

Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Claims (16)

1. A method for manufacturing a plurality host bus adapters, the method comprising:

generating a plurality of customized memory image files each customized with information unique to a corresponding host bus adapter of the plurality of host bus adapters wherein each customized memory image file includes a common portion common to each of the plurality of customized memory image files and a unique portion containing the information unique to the corresponding host bus adapter; and

programming a programmable memory device integral with each host bus adapter using a customized memory image file corresponding with said each host bus adapter,

wherein the step of programming is operable using means other than the corresponding said each host bus adapter.

2. The method of claim 1

wherein the step of generating further comprises:

adding unique information comprising a supplied SAS address for a particular host bus adapter to an un-customized memory image file to generate the customized memory image file corresponding to the particular host bus adapter.

3. The method of claim 1

wherein the step of generating further comprises:

adding unique information comprising a supplied board trace number for a particular host bus adapter to an un-customized memory image file to generate the customized memory image file corresponding to the particular host bus adapter.

4. The method of claim 1

wherein the step of generating further comprises:

adding unique information comprising a supplied configuration page for a particular host bus adapter to an un-customized memory image file to generate the customized memory image file corresponding to the particular host bus adapter.

5. The method of claim 1

wherein the step of generating further comprises:

adding unique information comprising a supplied boot record for a particular host bus adapter to an un-customized memory image file to generate the customized memory image file corresponding to the particular host bus adapter.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2009
From: FAULHABER, STEVEN F.; SINYKIN, JOSHUA P.; FREEL, MATTHEW K.
To: LSI CORPORATION
Reel/Frame 022154/0048 →