Low RC local clock distribution
View Patent ↗A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors.
1. A method of producing a low RC local clock distribution structure comprising:
arranging a plurality of buffers in a local gain buffer pair configuration;
connecting a conductor corresponding to a clock signal to an input of the local gain buffer pair;
connecting a shorting bar to an output of the local gain buffer pair; and
connecting a plurality of conductors to the shorting bar.
2. The method of claim 1 , wherein the local gain buffer pair corresponds to a second buffer and a third buffer as part of a three-stage fan-out 4 local gain configuration.
3. The method of claim 2 , wherein a RC skew of the three-stage fan-out 4 local gain configuration is smaller than that of a corresponding conventional fan-out 4 configuration.
4. The method of claim 1 , wherein a resistance of the conductor is smaller than that of a corresponding conductor in a conventional fan-out 4 configuration.
5. The method of claim 1 , wherein the shorting bar is an effective short when a sum of a skew from a last common ancestor added to a structural skew is less than a transition time of a shorted node corresponding to the shorting bar.
6. A low RC skew local clock distribution structure comprising:
a conductor;
a first clock signal incident on the conductor;
a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal; and
a shorting bar that shorts the second clock signal to a plurality of conductors.
7. The low RC skew local clock distribution structure of claim 6 , wherein the local gain buffer pair corresponds to a second and a third buffer as part of a three-stage fan-out 4 local gain configuration.
8. The low RC skew local clock distribution structure of claim 7 , wherein a RC skew of the three-stage fan-out 4 local gain configuration is smaller than that of a conventional fan-out 4 configuration.
9. The low RC skew local clock distribution structure of claim 6 , wherein a resistance of the conductor is smaller than that of a conventional fan-out 4 configuration.
10. The low RC skew local clock distribution structure of claim 6 , wherein the shorting bar is an effective short when a sum of a skew from a last common ancestor added to a structural skew is less than a transition time of a shorted node corresponding to the shorting bar.
11. A semiconductor device comprising:
a semiconductor die; and
a clock distribution network that distributes a primary clock signal within the semiconductor die;
wherein the clock distribution network comprises a low RC local clock distribution structure,
the low RC local clock distribution structure comprises:
a conductor,
a first clock signal incident on the conductor that is a derivative of the primary clock signal,
a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and
a shorting bar that shorts the second clock signal to a plurality of conductors.
12. The semiconductor device of claim 11 , wherein the local gain buffer pair corresponds to a second and a third buffer as part of a three-stage fan-out 4 local gain configuration.
13. The semiconductor device of claim 12 , wherein a RC skew of the three-stage fan-out 4 local gain configuration is smaller than that of a conventional FO4 configuration.
14. The semiconductor device of claim 11 , wherein a resistance of the conductor is smaller than that of a conventional fan-out 4 configuration.
15. The semiconductor device of claim 11 , wherein the shorting bar is an effective short when a sum of a skew from a last common ancestor added to a structural skew is less than a transition time of a shorted node corresponding to the shorting bar.
16. A system comprising:
an input device;
an output device;
a printed circuit board; and
a semiconductor device comprising a semiconductor die;
wherein the semiconductor die comprises a clock distribution network that distributes a primary clock signal,
the clock distribution network comprises a low RC local clock distribution structure, and
the low RC local clock distribution structure comprises:
a conductor,
a first clock signal incident on the conductor,
a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and
a shorting bar that shorts the second clock signal to a plurality of conductors.
17. The system of claim 16 , wherein the local gain buffer pair corresponds to a second and a third buffer as part of a three-stage fan-out 4 local gain configuration.
18. The system of claim 17 , wherein a RC skew of the three-stage fan-out 4 local gain configuration is smaller than that of a conventional fan-out 4 configuration.
19. The system of claim 16 , wherein a resistance of the conductor is smaller than that of a conventional fan-out 4 configuration.
20. The system of claim 16 , wherein the shorting bar is an effective short when a sum of a skew from a last common ancestor added to a structural skew is less than a transition time of a shorted node corresponding to the shorting bar.