Multiple frequency state detection for serial I/O interfaces
View Patent ↗Technologies are described herein for assigning multiple frequency states within a serial I/O interface. Bits within the serial I/O stream may be placed in frequency states in addition to high and low logic states. Placing a serial I/O bit into a frequency state where the bit may be transitioned according to a set of allowed frequencies can extend the information represented by each bit slot of a cyclical data I/O bit stream beyond the typical two states of logic high and logic low. A transition counter may be provided for each bit slot of a serialized stream. Each transition counter may be incremented in response to the respective bit slot changing its state from its previous sampled state. A frequency state may be assigned to a bit slot in response to a respective transition counter range associated with that bit slot.
1. A serial interface module comprising:
a clock signal;
a frame signal;
a data signal; and
a state detector configured to
sample the data signal according to a sampling period associated with the clock signal,
establish a data cycle period based on the clock cycles between pulses within the frame signal,
provide a transition counter for each bit slot within the data cycle period,
increment each transition counter in response to the data signal during the respective bit slot of a first data cycle being in a different state than during the respective bit slot of a next data cycle,
accumulate transition counter increments over a specified collection period, and
assign a frequency state to the bit slot in response to the accumulated transitions.
2. The module of claim 1 , wherein the state detector is further configured to apply a tolerance range to each transition counter prior to assigning a frequency.
3. The module of claim 1 , wherein the state detector is further configured to assign an error state to a bit slot in response to detecting an undefined frequency state.
4. The module of claim 1 , wherein the state detector is further configured to assign a logic level state to a bit slot in response to detecting a frequency state of zero.
5. The module of claim 1 , wherein the state detector is further configured to assign an error state to a bit slot in response to detecting an initial change in frequency state.
6. The module of claim 1 , wherein the serial interface comprises an SGPIO interface.
7. The module of claim 1 , wherein the serial interface supports communication between a storage system host bus adapter and a storage system backplane.
8. The module of claim 1 , wherein the serial interface supports communicating information for operating light emitting diodes associated with a data storage system.
9. The module of claim 8 , wherein the information relates to one of an activity state, a locate state, and a fail state associated with a mass storage device.
10. The module of claim 1 , wherein the serial interface is associated with an enclosure management controller within a data storage system.
11. A method for assigning multiple frequency states within a serial interface, the method comprising:
sampling a data signal of the serial interface according to a sampling period;
providing a transition counter for each bit slot within sampled data signal;
incrementing each transition counter in response to the sampled data signal during a respective bit slot being in a different state than during a previous sampling of the respective bit slot;
accumulating transition counter increments over a specified collection period; and
assigning a frequency state to the bit slot in response to the accumulated transitions.
12. The method of claim 11 , further comprising applying a tolerance range to each transition counter prior to assigning a frequency.
13. The method of claim 11 , further comprising assigning an error state to a bit slot in response to detecting an undefined frequency state.
14. The method of claim 11 , further comprising assigning a logic level state to a bit slot in response to detecting a frequency state of zero.
15. The method of claim 11 further comprising assigning an error state to a bit slot in response to detecting an initial change in frequency state.
16. The method of claim 11 , wherein the serial interface comprises an SGPIO interface.
17. The method of claim 11 , wherein the serial interface supports communication between a storage system host bus adapter and a storage system backplane.
18. The method of claim 11 , wherein the serial interface supports communicating information for operating light emitting diodes associated with a data storage system.
19. The method of claim 18 , wherein the information relates to one of an activity state, a locate state, and a fail state associated with a mass storage device.
20. A data storage system comprising:
a storage backplane supporting the connection of one or more mass storage devices;
a serial general purpose input/output interface configured to support communications between the storage backplane and a host bus adapter; and
a receiver associated with the serial general purpose input/output interface, the receiver configured to
sample a data signal of the serial general purpose input/output interface,
provide a transition counter for each bit slot within the sampled data signal,
increment each transition counter in response to the sampled data signal during a respective bit slot being in a different state than during a previous sampling of the respective bit slot,
accumulate transition counter increments over a specified collection period,
apply a tolerance range to each transition counter, and
assign a frequency state to each bit slot in response to the tolerance range of the accumulated transitions.