Integrated frequency calibration architecture
View Patent ↗In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuning voltage for the free running VCO is adjusted to offset any tuning error. In addition, in various embodiments a reference crystal oscillator used in the phase lock loop is located on a DSP module instead of on the RF module. In yet another exemplary embodiment, the free running VCO is the only high frequency VCO on a radio frequency module.
1. An integrated frequency calibration architecture comprising:
a radio frequency (RF) module in communication with a digital signal processor (DSP) module, wherein the RF module is located on an integrated circuit;
a voltage controlled oscillator (VCO) on the RF module, wherein the VCO is configured to have a normal operation mode and a frequency calibration mode;
a phase lock loop (PLL) on the RF module, wherein the PLL provides a VCO input voltage to the VCO based on a scaled reference frequency during the frequency calibration mode;
a VCO tuning circuit comprising a digital-to-analog converter (DAC), wherein the DAC adjusts to the VCO input voltage during the frequency calibration mode, and wherein the DAC connects to the VCO during the normal operation mode; and
a switch configured to switch the VCO between the normal operation mode and the frequency calibration mode.
2. The integrated frequency calibration architecture of claim 1 , wherein the switch is controlled by an enable signal from the DSP module.
3. The integrated frequency calibration architecture of claim 1 , wherein the VCO tuning circuit is located on the DSP module.
4. The integrated frequency calibration architecture of claim 1 , wherein the VCO tuning circuit is located on the RF module.
5. The integrated frequency calibration architecture of claim 1 , wherein the integrated circuit is a monolithic microwave integrated circuit (MMIC).
6. The integrated frequency calibration architecture of claim 5 , wherein the MMIC is configured for use in a radar system.
7. The integrated frequency calibration architecture of claim 1 , further comprising a database configured to store an oscillating frequency of the VCO and a corresponding tuning voltage of the DAC.
8. The integrated frequency calibration architecture of claim 1 , wherein the PLL comprises:
a dual-modulus prescaler and a control counter configured to reduce a VCO output frequency to generate a reduced VCO output frequency; and
a reference divider configured to receive a reference frequency from a reference oscillator and generate the scaled reference frequency; and
a phase/frequency detector configured to compare the scaled reference frequency and the reduced VCO output frequency of the VCO;
wherein the phase/frequency detector outputs a difference voltage configured to adjust the VCO output frequency during the frequency calibration mode.
9. The integrated frequency calibration architecture of claim 8 , wherein the reference oscillator is a crystal oscillator.
10. The integrated frequency calibration architecture of claim 9 , wherein the crystal oscillator is located on the RF module.
11. The integrated frequency calibration architecture of claim 9 , wherein the crystal oscillator is not located on the RF module, and wherein the crystal oscillator is a digital signal processor clock.
12. The integrated frequency calibration architecture of claim 1 , wherein the VCO is a high frequency VCO, and wherein the VCO is the only high frequency VCO on the RF module, and wherein high frequency is a frequency of 10 GHz or more.
13. A method of frequency calibration of a voltage controlled oscillator (VCO) on an integrated circuit, the method comprising:
phase locking, on the integrated circuit, the VCO based on a reference frequency and a VCO output frequency and generating a VCO input voltage; and
adjusting an output voltage of a digital-to-analog converter (DAC) to match the VCO input voltage during a frequency calibration mode and to generate an adjusted DAC output voltage;
wherein the adjusted DAC output voltage provides the VCO input voltage during a normal operating mode.
14. The method of claim 13 , further comprising:
comparing, during the normal operating mode, the VCO input voltage with the adjusted DAC output voltage using a difference amplifier, wherein the difference amplifier generates an offset error voltage; and
correcting the adjusted DAC output voltage by the offset error voltage, wherein the correcting is configured to compensate for an offset error of the DAC.
15. The method of claim 14 , further comprising correcting a stored DAC output voltage by the offset error voltage.
16. The method of claim 13 , further comprising repeating the method with another programming frequency.
17. The method of claim 13 , wherein the reference frequency is generated by a crystal oscillator.
18. The method of claim 13 , wherein the VCO is a high frequency VCO, and wherein the VCO is the only high frequency VCO on a radio frequency (RF) module, and wherein high frequency is a frequency of 10 GHz or more.
19. The method of claim 13 , wherein the adjusted DAC output voltage and the corresponding VCO output frequency are stored in a reference table in response to the adjusted DAC output voltage substantially equaling the VCO input voltage based on the reference frequency.
20. A method of frequency calibration of a voltage controlled oscillator (VCO), the method comprising:
phase locking the VCO based on a reference frequency and a VCO output frequency and generating a VCO input voltage; and
adjusting an output voltage of a digital-to-analog converter (DAC) to match the VCO input voltage during a frequency calibration mode and to generate an adjusted DAC output voltage;
wherein the adjusted DAC output voltage provides the VCO input voltage during a normal operating mode;
comparing the adjusted DAC output voltage and the VCO input voltage during the normal operating mode to measure a comparator offset voltage error; and
re-adjusting the output voltage of the DAC to match a combination of the VCO input voltage and the comparator offset voltage error to re-generate the adjusted DAC output voltage.