IP Library Granted Patent US 7,974,049
Granted Patent B2
US 7,974,049 · App. 12/363,877 · Granted Jul 5, 2011

Over-current protection in linear regulators

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Quick Facts
Patent No.
US 7,974,049
App. No.
12/363,877
Granted
Jul 5, 2011
Kind
B2
Abstract

An integrated circuit radio transceiver and method therefor includes a linear regulator an output transistor for producing a current into an output node of the regulator wherein an amplification block is operable to produce a bias signal to a gate terminal of the output transistor to operably bias the output transistor to produce the current into the output node of the regulator. A current steering amplification block is operably disposed to steer current in/out of the gate of the output transistor (depending on device type) based upon the current being conducted through the output node of the regulator exceeding a specified threshold. The current steering amplification block further includes a current sinking element operably disposed to sink a specified amount of current to define the specified threshold.

Claims (27)

1. An integrated circuit linear regulator operably disposed to regulate a power supply for generating power, comprising:

a regulator;

an over-current protection block, comprising:

an output transistor operably disposed to produce a limited output signal to the regulator;

an amplification block for producing a bias signal for the output transistor; and

a current steering amplification block for generating a limiting bias signal to adjust and limit the bias signal to the output transistor whenever an output current magnitude of an output current exceeds a threshold.

2. The integrated circuit linear regulator of claim 1 wherein the limiting bias signal substantially replaces the bias signal to limit the output current produced by the output transistor.

3. The integrated circuit linear regulator of claim 1 wherein the limiting bias signal reduces the bias signal to limit the output current produced by the output transistor.

4. The integrated circuit linear regulator of claim 1 wherein the current steering amplification block is biased into an off condition during normal operation of the linear regulator.

5. The integrated circuit linear regulator of claim 1 wherein the current steering amplification block is biased into an on condition whenever the output current magnitude of the output current exceeds the specified threshold wherein the current steering amplification block is operable to sink excess current produced by the amplification block during the low impedance output condition.

6. The integrated circuit linear regulator of claim 1 wherein the current steering amplification block comprises amplification circuitry that is operably disposed to bias into an on state whenever the output current reaches the specified threshold through the output transistor.

7. The integrated circuit linear regulator of claim 6 wherein the specified threshold is based at least partially upon a current source disposed within the current steering amplification block.

8. The integrated circuit linear regulator of claim 6 wherein the specified threshold is at least partially based upon a resistor disposed within the current steering amplification block, which resistor defines a current level specified by a reference voltage divided by the resistor.

9. The integrated circuit linear regulator of claim 1 comprising similar first and second current mirrors disposed within the amplification block and within the current steering amplification block respectively, the first and second current mirrors having a commonly connected output node further connected to a gate terminal of the output transistor.

10. The integrated circuit linear regulator of claim 1 wherein the linear regulator is operably disposed to regulate the power supply for generating power to at least a portion of one of a transmitter and a receiver front end of an integrated circuit radio transceiver.

11. A method for an integrated circuit linear regulator, comprising:

producing a current into an output node of a regulator circuit;

producing a bias signal to a gate terminal of an output transistor of the regulator circuit to operably bias the output transistor to produce the current into the output node of the regulator circuit;

steering current out of the gate of the output transistor based upon the current being conducted through the output node of the regulator circuit exceeding a specified threshold by sinking current through a current sinking element operably disposed to sink a specified amount of current to define the specified threshold, including producing a current steering transconductance device bias signal.

12. The method of claim 11 wherein the current sinking element comprises one of a current source or a resistive element.

13. The method of claim 11 further including decreasing a bias signal for the output transistor to limit an output current level of the integrated circuit linear regulator.

14. A method for regulating an output current level of a regulator, comprising:

producing current from a first current mirror into a first transconductance amplifier;

biasing an output transistor with an output signal produced by the first transconductance amplifier;

biasing current steering logic into an operative state and reducing the bias on the output transistor whenever the output signal exceeds a specified threshold; and

biasing a current steering transconductance device into an operative state and sinking current through the current steering transconductance device that is produced by a second current mirror.

15. The method of claim 14 further including producing, at an output of the second current mirror, a limiting bias signal that is summed with the output signal to operatively reduce the bias to the output transistor and the steering amplifier biasing transistor.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →