Patent Application

App. No. 12/363,916

Abstract

Claims (41)

1 . A method for fabricating a transducer comprising:

providing a handle wafer structure comprising a first substrate layer and a first patterned metal layer formed on a first surface of the first substrate layer to define a bottom capacitive sensing electrode, a first interconnect anchor structure, and a first sealing ring structure;

providing an active wafer structure comprising a second substrate layer and a second patterned metal layer formed on a first surface of the second substrate layer to define a second interconnect anchor structure and a second sealing ring structure;

placing the active wafer structure on the handle wafer structure so that the first and second interconnect anchor structures are aligned and so that the first and second sealing ring structures are aligned;

bonding the handle wafer structure to the active wafer structure using metal thermocompression bonding to form a bond between the first and second interconnect anchor structures and between the first and second sealing ring structures;

forming a third patterned layer on a second, opposite surface of the second substrate layer to define a third interconnect anchor structure and a third sealing ring structure;

providing a cap wafer structure comprising a third substrate layer and a fourth patterned metal layer formed on a first surface of the third substrate layer to define an upper capacitive sensing electrode, a fourth interconnect anchor structure and a fourth sealing ring structure;

placing the cap wafer structure on the active wafer structure so that the third and forth interconnect anchor structures are aligned and so that the third and fourth sealing ring structures are aligned; and

bonding the cap wafer structure to the active wafer structure to form a bond between the third and fourth interconnect anchor structures and between the third and fourth sealing ring structures, thereby providing a hermetic enclosure surrounding at least part of the active wafer structure.

2 . The method of claim 1 , where providing the handle wafer structure comprises providing a first monocrystalline silicon substrate layer on which is formed a first patterned aluminum layer to define the bottom capacitive sensing electrode, first interconnect anchor structure, and first sealing ring structure.

3 . The method of claim 1 , where providing the active wafer structure comprises providing a second monocrystalline silicon substrate layer on which is formed a second patterned aluminum layer to define the second interconnect anchor structure and a second sealing ring structure.

4 . The method of claim 1 , where bonding the handle wafer structure to the active wafer structure comprises:

heating the handle wafer structure and the active wafer structure; and

compressing the handle wafer structure and the active wafer structure against each other to form the bond between the first and second interconnect anchor structures and between the first and second sealing ring structures.

5 . The method of claim 1 , where forming a third patterned layer comprises forming a patterned aluminum layer on the second, opposite surface of the second substrate layer to define the third interconnect anchor structure and a third sealing ring structure.

6 . The method of claim 5 , where bonding the cap wafer structure to the active wafer structure comprises aluminum-aluminum thermocompression bonding to form a bond between the third and fourth interconnect anchor structures and between the third and fourth sealing ring structures.

7 . The method of claim 1 , where forming a third patterned layer comprises forming a patterned germanium layer on the second, opposite surface of the second substrate layer to define the third interconnect anchor structure and a third sealing ring structure.

8 . The method of claim 7 , where bonding the cap wafer structure to the active wafer structure comprises aluminum-germanium eutectic bonding to form a bond between the third and fourth interconnect anchor structures and between the third and fourth sealing ring structures.

9 . The method of claim 1 , further comprising etching the active wafer structure with a deep reactive ion etch process to form a high aspect ratio sensing subassembly from the active wafer structure prior to bonding the cap wafer structure to the active wafer structure.

10 . A method for fabricating a high aspect ratio transducer, comprising:

compression bonding a handle wafer structure to an active wafer structure so that metallic interconnect and anchor elements on a first surface of the handle wafer structure are aligned to corresponding metallic interconnect and anchor elements on a first surface of the active wafer structure, where the handle wafer structure comprises a first out-of-plane sensing electrode on the first surface of the handle wafer structure;

selectively etching the active wafer structure to form a high aspect ratio proof mass element which is aligned with the first out-of-plane sensing electrode and to form semiconductor interconnect and anchor elements which are aligned with the metallic interconnect and anchor elements on the first surface of the active wafer structure; and

bonding a cap wafer structure to the active wafer structure so that metallic interconnect and anchor elements on a first surface of the cap wafer structure are aligned to corresponding interconnect and anchor elements on a second surface of the active wafer structure, where the cap wafer structure comprises a second out-of-plane sensing electrode on the first surface of the cap wafer structure that is aligned with the high aspect ratio proof mass element.

11 . The method of claim 10 , where compression bonding the handle wafer structure to the active wafer structure comprises:

heating the handle wafer structure and the active wafer structure; and

compressing the handle wafer structure and the active wafer structure against each other to bond the metallic interconnect and anchor elements on the first surface of the handle wafer structure to the corresponding metallic interconnect and anchor elements on the first surface of the active wafer structure.

12 . The method of claim 10 , where compression bonding the handle wafer structure to the active wafer structure comprises compression bonding the handle wafer structure comprising a first monocrystalline silicon substrate layer to the active wafer structure comprising a second monocrystalline silicon substrate layer, where a first patterned aluminum layer is formed on the first monocrystalline silicon substrate layer to define the first out-of-plane sensing electrode and the metallic interconnect and anchor elements on the first surface of the handle wafer structure, and where a second patterned aluminum layer is formed on the second monocrystalline silicon substrate layer to define the metallic interconnect and anchor elements on the first surface of the active wafer structure.

13 . The method of claim 10 , where selectively etching the active wafer structure comprises selectively applying a deep reactive ion etch process to form the high aspect ratio proof mass element and the semiconductor interconnect and anchor elements.

14 . The method of claim 10 , further comprising forming the corresponding interconnect and anchor elements on the second surface of the active wafer structure as metallic interconnect and anchor elements on the second surface of the active wafer structure that are aligned with the metallic interconnect and anchor elements on the first surface of the active wafer structure prior to selectively etching the active wafer structure.

15 . The method of claim 14 , where bonding the cap wafer structure to the active wafer structure comprises compression bonding the cap wafer structure to the active wafer structure so that the metallic interconnect and anchor elements on the first surface of the cap wafer structure are aligned with the metallic interconnect and anchor elements on the second surface of the active wafer structure.

16 . The method of claim 10 , further comprising forming the corresponding interconnect and anchor elements on the second surface of the active wafer as semiconductor interconnect and anchor elements on the second surface of the active wafer structure that are aligned with the metallic interconnect and anchor elements on the first surface of the active wafer structure prior to selectively etching the active wafer structure.

17 . The method of claim 16 , where bonding the cap wafer structure to the active wafer structure comprises eutectic bonding the cap wafer structure to the active wafer structure so that the metallic interconnect and anchor elements on the first surface of the cap wafer structure are aligned with the semiconductor interconnect and anchor elements on the second surface of the active wafer structure.

18 . The method of claim 17 , where eutectic bonding comprises gold and tin eutectic bonding, gold and germanium eutectic bonding, aluminum and germanium eutectic bonding or gold and silicon eutectic bonding.

19 . The method of claim 10 , further comprising back grinding the active wafer structure to a predetermined thickness prior to selectively etching the active wafer structure to allow a high aspect ratio MEMS proof mass element to be formed from the active wafer structure.

20 . A high aspect ratio transducer, comprising:

a first monocrystalline semiconductor substrate structure comprising a first patterned metallic layer defining a first out-of-plane sensing electrode and one or more metallic interconnect structures on a first surface of the first monocrystalline semiconductor substrate structure;

a second monocrystalline semiconductor substrate structure comprising:

a second patterned metallic layer on a first surface of the second monocrystalline semiconductor substrate structure defining one or more metallic interconnect structures that are thermocompression bonded to the one or more metallic interconnect structures on the first surface of the first monocrystalline semiconductor substrate structure;

a high aspect ratio proof mass element which is aligned with the first out-of-plane sensing electrode; and

a third patterned metallic or semiconductor layer on a second surface of the second monocrystalline semiconductor substrate structure defining one or more metallic or semiconductor interconnect structures on the second surface of the second monocrystalline semiconductor substrate structure; and

a third monocrystalline semiconductor substrate structure comprising a fourth patterned metallic layer defining a second out-of-plane sensing electrode that is aligned with the high aspect ratio proof mass element and defining one or more metallic interconnect structures on a first surface of the third monocrystalline semiconductor substrate structure that are bonded to the one or more metallic or semiconductor interconnect structures on the second surface of the second monocrystalline semiconductor substrate structure.

Assignments (14)