IP Library Granted Patent US 8,084,826
Granted Patent B2
US 8,084,826 · App. 12/364,797 · Granted Dec 27, 2011

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 8,084,826
App. No.
12/364,797
Granted
Dec 27, 2011
Kind
B2
Abstract

An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.

Claims (38)

1. A semiconductor device, comprising:

a semiconductor substrate;

an element isolation region for electrically isolating a first active region in an N-channel region from a second active region in a P-channel region in the semiconductor substrate;

an n-channel field effect transistor having an n-channel gate formed on the first active region with a gate insulating film interposed therebetween and a first source/drain region formed on both sides of the n-channel gate in the first active region;

a p-channel field effect transistor having a p-channel gate formed on the second active region with a gate insulating film interposed therebetween and a second source/drain region formed on both sides of the p-channel gate in the second active region;

an n-channel contact liner formed over the first active region and side surfaces and a top surface of the n-channel gate and having a shrinkage force;

a p-channel contact liner formed over the second active region and side surfaces and a top surface of the p-channel gate, formed continuously with the n-channel contact liner so as to have a larger thickness than that of the n-channel contact liner, and having an expansion force; and

a contact liner formed between the first active region and n-channel field effect transistor and the n-channel contact liner and between the second active region and p-channel field effect transistor and the p-channel contact liner, wherein:

the n-channel contact liner and the p-channel contact liner are made of a same base material and contain different impurity atoms from each other, and

the contact liner is made of the same base material as that of the n-channel contact liner and the p-channel contact liner and has a smaller density of the impurity atoms than that of the impurity atoms in the n-channel contact liner and the p-channel contact liner.

2. The semiconductor device according to claim 1 , wherein the base material of the n-channel contact liner and the p-channel contact liner is silicon nitride and a density of Si—N bonds in the n-channel contact liner is higher than that of Si—N bonds in the p-channel contact liner.

3. The semiconductor device according to claim 1 , wherein the n-channel contact liner contains carbon or fluorine as the impurity atoms.

4. The semiconductor device according to claim 1 , wherein the p-channel contact liner contains oxygen as the impurity atoms.

5. The semiconductor device according to claim 1 , wherein the n-channel contact liner and the p-channel contact liner contain an element having an ionic radius equal to or larger than that of silicon at a higher concentration than that in the contact liner.

6. The semiconductor device according to claim 5 , wherein the n-channel contact liner and the p-channel contact liner contain silicon, arsenic, indium, or germanium at a higher concentration than that in the contact liner.

7. The semiconductor device according to claim 1 , wherein the p-channel contact liner contains Ge at a higher density than that in the n-channel contact liner.

8. The semiconductor device according to claim 1 , wherein a density of Si—H bonds in the n-channel contact liner and the p-channel contact liner is higher than that of Si—H bonds in the contact liner.

9. The semiconductor device according to claim 1 , wherein a difference in level between the n-channel contact liner and the p-channel contact liner in a boundary region between the N-channel region and the P-channel region is 3 nm to 15 nm.

10. A semiconductor device, comprising:

a semiconductor substrate;

an element isolation region for electrically isolating a first active region in an N-channel region from a second active region in a P-channel region in the semiconductor substrate;

an n-channel field effect transistor having an n-channel gate formed on the first active region with a gate insulating film interposed therebetween and a first source/drain region formed on both sides of the n-channel gate in the first active region;

a p-channel field effect transistor having a p-channel gate formed on the second active region with a gate insulating film interposed therebetween and a second source/drain region formed on both sides of the p-channel gate in the second active region;

an n-channel contact liner formed over the first active region and side surfaces and a top surface of the n-channel gate and having a shrinkage force;

a p-channel contact liner formed over the second active region and side surfaces and a top surface of the p-channel gate-and having an expansion force; and

a boundary region formed between the n-channel contact liner and the p-channel contact liner, wherein

the p-channel contact liner has a larger thickness than that of the n-channel contact liner, and

the n-channel contact liner, the p-channel contact liner and the boundary region are formed continuously.

11. The semiconductor device according to claim 10 , wherein the n-channel contact liner and the p-channel contact liner are made of a same base material and contain different impurity atoms from each other.

12. The semiconductor device according to claim 11 , further comprising a contact liner formed between the first active region and n-channel field effect transistor and the n-channel contact liner and between the second active region and p-channel field effect transistor and the p-channel contact liner, wherein the contact liner is made of the same base material as that of the n-channel contact liner and the p-channel contact liner and has a smaller density of the impurity atoms than that of the impurity atoms in the n-channel contact liner and the p-channel contact liner.

13. The semiconductor device according to claim 12 , wherein the n-channel contact liner and the p-channel contact liner contain an element having an ionic radius equal to or larger than that of silicon at a higher concentration than that in the contact liner.

14. The semiconductor device according to claim 13 , wherein the n-channel contact liner and the p-channel contact liner contain silicon, arsenic, indium, or germanium at a higher concentration than that in the contact liner.

15. The semiconductor device according to claim 12 , wherein a density of Si—H bonds in the n-channel contact liner and the p-channel contact liner is higher than that of Si—H bonds in the contact liner.

16. The semiconductor device according to claim 10 , wherein a base material of the n-channel contact liner and the p-channel contact liner is silicon nitride and a density of Si—N bonds in the n-channel contact liner is higher than that of Si—N bonds in the p-channel contact liner.

17. The semiconductor device according to claim 10 , wherein the n-channel contact liner contains carbon or fluorine as impurity atoms.

18. The semiconductor device according to claim 10 , wherein the p-channel contact liner contains oxygen as impurity atoms.

19. The semiconductor device according to claim 10 , wherein the p-channel contact liner contains Ge at a higher density than that in the n-channel contact liner.

20. The semiconductor device according to claim 10 , wherein a difference in level between the n-channel contact liner and the p-channel contact liner in a boundary region between the N-channel region and the P-channel region is 3 nm to 15 nm.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2024
From: NUVOTON TECHNOLOGY CORPORATION JAPAN
To: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
Reel/Frame 068118/0314 →
CHANGE OF NAME Recorded Jun 12, 2024
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 067711/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2009
From: KANEGAE, KENSHI; YAMADA, MASARU
To: PANASONIC CORPORATION
Reel/Frame 022409/0422 →