IP Library Granted Patent US 7,981,804
Granted Patent B2
US 7,981,804 · App. 12/364,908 · Granted Jul 19, 2011

Manufacturing method of semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,981,804
App. No.
12/364,908
Granted
Jul 19, 2011
Kind
B2
Abstract

A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.

Claims (12)

1. A method of manufacturing a semiconductor device having a metal interconnection on a semiconductor substrate, comprising the steps of:

forming an interlayer insulating film on the semiconductor substrate;

forming a trench in the interlayer insulating film and the semiconductor substrate for forming a dummy metal interconnection, the trench having an opening whose diameter is twice or longer of a total film thickness of a metal film and a resist film the diameter having an aspect ratio in the range of 1 to 3;

forming a metal film on a surface of the interlayer insulating film and inside the trench by deposition;

forming a pattern with a resist on the metal film; and

etching the metal film to form the metal interconnection on the interlayer insulating film and the dummy metal interconnection inside and around the trench close to each other.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein; in the step of forming a pattern with a resist on the metal film, a part of the resist above the trench is exposed to reduce a thickness of the resist film.

3. A method of manufacturing a semiconductor device according to claim 2 , wherein; the exposed part of the resist above the trench is circular in plan view.

4. A method of manufacturing a semiconductor device according to claim 2 , wherein; the exposed part of the resist above the trench is quadrangular in plan view.

5. A method of manufacturing a semiconductor device according to claim 3 , wherein; a plurality of the circular exposed part of the resist is formed above a single trench.

6. A method of manufacturing a semiconductor device according to claim 4 , wherein; a plurality of the quadrangular exposed part of the resist is formed above a single trench.

7. A method of manufacturing a semiconductor device according to claim 1 , wherein; the metal film is formed from aluminum, or an aluminum alloy containing one out of silicon and copper.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2009
From: MURATA, MICHIHIRO
To: SEIKO INSTRUMENTS INC.
Reel/Frame 022533/0500 →