Thin film transistor and flat panel display device including the same
View Patent ↗A flat panel display device is disclosed. In one embodiment, the flat panel display device includes i) a semiconductor layer including a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and the groove is configured to separate the channel region from adjacent thin film transistors and ii) a stop layer formed below at least a portion of the semiconductor layer. According to one embodiment of the invention, a semiconductor layer can be easily patterned without using a dry or wet etching technique such as photolithography.
1. A flat panel display device comprising a thin film transistor, wherein the thin film transistor comprises:
a semiconductor layer formed over a substrate, wherein the semiconductor layer comprises a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and wherein the groove is configured to separate the channel region from adjacent thin film transistors; and
a stop layer formed below at least a portion of the semiconductor layer, wherein the stop layer contacts the source and drain electrodes, wherein the stop layer does not overlap with the channel region in a direction vertically extending from the substrate to the stop layer, wherein the stop layer is formed only below the groove and an immediate periphery thereof, and wherein the depth of the groove is at least equal to the thickness of the semiconductor layer.
2. The flat panel display device according to claim 1 , wherein the depth of the groove is greater than the thickness of the semiconductor layer and is less than the sum of the thickness of the semiconductor layer and the thickness of the stop layer.
3. The flat panel display device according to claim 1 , wherein the semiconductor layer and the stop layer are formed on the substrate, and wherein the stop layer is formed on the entire surface of the substrate except for a region between the source electrode and the drain electrode where the channel region is formed.
4. The flat panel display device according to claim 1 , wherein the semiconductor layer and the stop layer are formed on the substrate, and wherein the stop layer is formed on the entire surface of the substrate except for regions corresponding to end portions of the source electrode and the drain electrode, the end portions facing each other.
5. The flat panel display device according to claim 1 , wherein the depth of the groove is substantially equal to the sum of the thickness of the semiconductor layer and the thickness of the stop layer.
6. The flat panel display device according to claim 5 , wherein the semiconductor layer and the stop layer are formed on the substrate, and wherein the stop layer is formed on the entire surface of the substrate except for the groove and a region between the source electrode and the drain electrode where the channel region is formed.
7. The flat panel display device according to claim 5 , wherein the semiconductor layer and the stop layer are formed on the substrate, and wherein the stop layer is formed on the entire surface of the substrate except for the groove and regions corresponding to end portions of the source electrode and the drain electrode, the end portions facing each other.
8. The flat panel display device according to claim 1 , wherein the groove forms a closed curve.
9. The flat panel display device according to claim 8 , wherein the channel region is located inside the close curve.
10. The flat panel display device according to claim 9 , further comprising a gate electrode and a gate insulating film covering the gate electrode to insulate the source electrode, the drain electrode and the semiconductor layer from the gate electrode, wherein the source electrode, the drain electrode and the channel region are formed on the gate electrode, and wherein the semiconductor layer covers the source electrode and the drain electrode.
11. The flat panel display device according to claim 1 , wherein the groove forms at least a pair of parallel lines.
12. The flat panel display device according to claim 11 , wherein the channel region is located between the at least one of the pairs of the parallel lines.
13. The flat panel display device according to claim 1 , wherein the semiconductor layer is formed of an organic material.
14. The flat panel display device according to claim 1 , further comprising a gate electrode and a gate insulating film that insulate the gate electrode from the semiconductor layer and is interposed between the gate electrode and the semiconductor layer, wherein the semiconductor layer covers the source electrode and the drain electrode, and wherein the gate electrode is formed on the semiconductor layer.
15. The flat panel display device according to claim 1 , wherein the stop layer is formed as a priming layer which is cracked when irradiated with light or when heat is applied thereto.
16. The flat panel display device according to claim 15 , wherein the stop layer is formed of organic materials having an organic acceptor selected from the group consisting of 4-Nitroaniline, 2,4-dinitronapthalene, 2-Amino-5-nitrobenzonitrile, 9,10-dicyanoanthracene, 2,4-dinitrophenylamine, and 2,4-dinitroaniline.
17. The flat panel display device according to claim 1 , wherein the semiconductor layer and the stop layer are formed on the substrate, wherein each of the source and drain electrodes comprises bottom and top portions, wherein the bottom portions are closer to the substrate than the top portion, and wherein the stop layer contacts one of i) the bottom portions and ii) top portions of the source and drain electrodes.