METHOD TO ACCELERATE NULL-TERMINATED STRING OPERATIONS

1 . A method executed by a processor, comprising:

reading a first register value, wherein the first register value comprises at least two bytes;

reading a second register value, wherein the second register value comprises at least two bytes,

wherein the first register value and the second register value both comprise the same number of bytes;

comparing the bytes of the first register value with the bytes of the second register value;

setting a third register to indicate a match if

(1) a byte in the first register value is equal to a corresponding byte in the second register value, or

(2) if a byte in the first register value is zero; and

setting a fourth register value to

(1) a count of the matching byte, if the byte in the first register value is equal to the corresponding byte in the second register value, or

(2) a number outside of a range of values comprising numbers between 0 and n−1, if the byte in the first register value is not equal to the corresponding byte in the second register value,

wherein n is an integer corresponding to the number of bytes in the first and second register values.

2 . The method of claim 1 , wherein the bytes of the first register value and the second register value are compared from the most significant byte to the least significant byte, if the processor is big-endian.

3 . The method of claim 1 , wherein the bytes of the first register value and the second register value are compared from the least significant byte to the most significant byte, if the processor is little-endian.

4 . The method of claim 1 , wherein the third register is a condition flag register comprising one bit.

5 . The method of claim 1 , wherein:

the third register is a condition register comprising a plurality of bits, and

one bit of the third register is set to indicate the match.

6 . The method of claim 1 , wherein:

the third register is a condition register comprising a plurality of bits, and

the third register is set to a first match value when a determination is made that a byte in the first register value is equal to a corresponding byte in the second register value, otherwise the third register is set to a second match value when a byte in the first register value is zero.

7 . The method of claim 1 , wherein the fourth register value is set to −1, if the byte in the first register value is not equal to the corresponding byte in the second register value.

8 . The method of claim 1 , wherein the third register and the fourth register values are set simultaneously.

9 . The method of claim 1 , wherein at least two separate registers cooperate with the processor to execute the method.

10 . The method of claim 1 , wherein the processor loads into a register beginning with a predetermined byte boundary.

11 . The method of claim 1 , wherein the bytes of the first register value are compared with only the lowest bytes of the second register value.

12 . The method of claim 1 , further comprising:

modifying the third register if a match is not indicated.

13 . The method of claim 12 , wherein:

the third register is a condition flag register comprising one bit,

the bit is set when the match is indicated, and

the bit is cleared when the match is not indicated.

14 . The method of claim 12 , wherein:

the third register is a condition flag register comprising one bit,

the bit is cleared when the match is indicated, and

the bit is set when the match is indicated.

15 . The method of claim 12 , wherein:

the third register is a condition register comprising a plurality of bits,

one of the plurality of bits is set when the match is indicated, and

the one bit is cleared when the match is not indicated.

16 . The method of claim 12 , wherein:

the third register is a condition register comprising a plurality of bits,

one of the plurality of bits is cleared when the match is indicated, and

the one bit is set when the match is not indicated.

17 . A method executed by a processor, comprising:

reading a first register value, wherein the first register value comprises at least two bytes;

reading a second register value, wherein the second register value comprises at least two bytes,

wherein the first register value and the second register value both comprise the same number of bytes;

comparing the bytes of the first register value with the bytes of the second register value;

setting a third register to indicate a match if

(1) a byte in the first register value is not equal to a corresponding byte in the second register value, or

(2) if a byte in the first register value is zero; and

setting a fourth register value to

(1) a count of the matching byte, if the byte in the first register value is not equal to the corresponding byte in the second register value, or

(2) a number outside of a range of values comprising numbers between 0 and n−1, if the byte in the first register value is equal to the corresponding byte in the second register value,

wherein n is an integer corresponding to the number of bytes in one of either the first and second registers.

18 . The method of claim 17 , wherein the bytes of the first register value and the second register value are compared from the most significant byte to the least significant byte, if the processor is big-endian.

19 . The method of claim 17 , wherein the bytes of the first register value and the second register value are compared from the least significant byte to the most significant byte, if the processor is little-endian.

20 . The method of claim 17 , wherein the third register is a condition flag register comprising one bit.

21 . The method of claim 17 , wherein:

the third register is a condition register that comprises a plurality of bits, and

one bit of the third register is set to indicate the match.

22 . The method of claim 17 , wherein:

the third register is a condition register comprising a plurality of bits, and

the third register is set to a first match value when a determination is made that a byte in the first register value is not equal to a corresponding byte in the second register value, otherwise the third register is set to a second match value when a byte in the first register value is zero.

23 . The method of claim 17 , wherein the fourth register value is set to −1, if the byte in the first register value is not equal to the corresponding byte in the second register value.

24 . The method of claim 17 , wherein the third register and the fourth register values are set simultaneously.

25 . The method of claim 17 , wherein at least two separate registers cooperate with the processor to execute the method.

26 . The method of claim 17 , wherein the processor loads into a register beginning with a predetermined byte boundary.

27 . The method of claim 17 , wherein the bytes of the first register value are compared only with the lowest bytes of the second register value.

28 . The method of claim 17 , further comprising:

modifying the third register if a match is not indicated.

29 . The method of claim 28 , wherein:

the third register is a condition flag register comprising one bit,

the bit is set when the match is indicated, and

the bit is cleared when the match is not indicated.

30 . The method of claim 28 , wherein:

the third register is a condition flag register comprising one bit,

the bit is cleared when the match is indicated, and

the bit is set when the match is indicated.

31 . The method of claim 28 , wherein:

the third register is a condition register comprising a plurality of bits,

one of the plurality of bits is set when the match is indicated, and

the one bit is cleared when the match is not indicated.

32 . The method of claim 28 , wherein:

the third register is a condition register comprising a plurality of bits,

one of the plurality of bits is cleared when the match is indicated, and

the one bit is set when the match is not indicated.