Array substrate and display device
View Patent ↗In the array substrate where the display region has the non-quadrangle shape, a sub-capacitance line which forms a sub-capacitance is disposed at the pixel, a intersection region of the scanning lead-out line and a signal lead-out line is located at the frame region on the outside of the display region, a common lead-out line which connects the sub-capacitance line in common is disposed at the frame region side where the scanning lead-out line is disposed, the common lead-out line is not disposed in the intersection region, but disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line.
1. An array substrate comprising:
a pixel that is provided on the array substrate, the pixel comprising:
a scanning line;
a signal line that intersects the scanning line;
a thin film transistor that is connected to the scanning line and the signal line in a region surrounded by the scanning line and the signal line;
a pixel electrode that is connected to the thin film transistor; and
a sub-capacitance line that forms a sub-capacitance,
wherein a display region, where a plurality of the pixels is disposed in a matrix-like shape, has a non-quadrangle shape,
wherein a frame region on the outside of a display region comprises:
a scanning lead-out line connected to the scanning line;
a signal lead-out line connected to the signal line; and
a common lead-out line that connects the sub-capacitance line in common to a side of a frame region where the scanning lead-out line is disposed,
wherein the frame region comprises an intersection region of the scanning lead-out line and the signal lead-out line, and
wherein the common lead-out line is disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line, whereas the common lead-out line is not disposed in the intersecting region.
2. The array substrate according to claim 1 ,
wherein the common lead-out line is configured as a lamination structure, in which the common lead-out line is connected with a sub-common lead-out line via a contact hole, the sub-common lead-out line being made of the same layer as the pixel electrode.
3. A display device comprising:
an array substrate comprising:
a pixel that is provided on the array substrate, the pixel comprising:
a scanning line;
a signal line that intersects the scanning line;
a thin film transistor that is connected to the scanning line and the signal line in a region surrounded by the scanning line and the signal line;
a pixel electrode that is connected to the thin film transistor; and
a sub-capacitance line that forms a sub-capacitance,
wherein a display region, where a plurality of the pixels is disposed in a matrix-like shape, has a non-quadrangle shape,
wherein a frame region on the outside of a display region comprises:
a scanning lead-out line connected to the scanning line;
a signal lead-out line connected to the signal line; and
a common lead-out line that connects the sub-capacitance line in common to a side of a frame region where the scanning lead-out line is disposed,
wherein the frame region comprises an intersection region of the scanning lead-out line and the signal lead-out line, and
wherein the common lead-out line is disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line, whereas the common lead-out line is not disposed in the intersecting region; and
a display medium which is combined with the array substrate.